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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/56370完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢 | |
| dc.contributor.author | Ying-Chen Liu | en |
| dc.contributor.author | 劉映辰 | zh_TW |
| dc.date.accessioned | 2021-06-16T05:25:29Z | - |
| dc.date.available | 2019-08-17 | |
| dc.date.copyright | 2014-08-17 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-08-14 | |
| dc.identifier.citation | [1] B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2003.
[2] C. R. Hogge, “A Self-Correcting Clock Recovery Circuit,” IEEE J. Lightwave Tech., vol. 3, no. 12, pp. 1312-1314, Dec. 1985. [3] J. D. H. Alexander, “Clock Recovery from Random Binary Signals,” Electronics Letters, vol. 11, pp. 541-542, Oct. 1975. [4] H. Wang and R. Nottenburg, “A 1Gb/s CMOS Clock and Data Recovery Circuit,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 354-355, Feb. 1999. [5] A. Pottbacker, U. Langmann, and H. Schreiber, “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction Up to 8 Gb/s,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1747–1751, Dec. 1992. [6] J. C. Scheeytt, G. Hanke, and U. Langmann, “A 0.155-0.622, and 2.488 Gb/s Automatic Bit-Rate Selecting Clock and Data Recovery IC for Bit-Rate Transparent SDH Systems,” IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1935–1943, Dec. 1999. [7] R. Kreienkamp, U. Langmann, C. Zimmermann, T. Aoyama, and H. Siedhoff, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with Analog Phase Interpolator,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 736–743, Mar. 2005. [8] M.Y. He and J. Poulton, “ A CMOS Mixed-Signal Clock and Data Recovery Circuit for OIF CEI-6G + Backplane Transceiver,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 597–606, Mar. 2006. [9] M. Hsieh, G. E. Sobelman “Clock and Data Recovery with Adaptive Loop Gain for Spread Spectrum SerDes Applications,” IEEE Int. Symposium on Circuits and Systems(ISCAS) , pp. 4883–4886, Mar. 2005. [10] D. Dalton, K. Chai, E. Evans, M. Ferriss, D. Hitchcox, P. Murray, S. Selvanayagam, P. Shepherd, and L. DeVito, “12.5 Mb/s to 2.7 Gb/s Continuous-Rate CDR with Automatic Frequency Acquisition and Data-Rate Readback” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2713–2725, Dec. 2005. [11] W. Rhee, H. Ainspan, S. Rylov, A. Rylyakov, M. Beakes, D. Friedman, S. Gowda, and M. Soyuer, “A 10 Gb/s CMOS Clock and Data Recovery Circuit Using a Secondary Delay-Locked Loop,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 81–84, Sept. 2003. [12] J. Kim and D. -K. Jeong “Multi-Gigabit-Rate Clock and Data Recovery Based on Blind Oversampling,” IEEE Communication Magazine, vol. 41, no. 12, pp. 68–74, Dec. 2003. [13] S. I. Ahmed and T. A. Kwasniewski, “Overview of Oversampling Clock and Data Recovery Circuits,” Canadian Conference on Electrical and Computer Engineering, pp. 1876–1881, May 2005. [14] R. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems,” in Phase-Locking in High-Performance Systems: From Devices to Architectures, B. Razavi, Ed. New York: Wiley-IEEE Press, 2003, pp. 34–45. [15] P. K. Hanumolu, G. –Y. Wei, and U. –K. Moon, “A Wide-Tracking Range Clock and Data Recovery Circuit,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 425-439, Feb. 2008. [16] W. Yin, R. Inti, A. Elshazly, M. Talegaonkar, B. Young, and P. K. Hanumolu, “A TDC-Less 7-mW 2.5-Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 3163-3173, Dec. 2011. [17] Y. H. Kwak, Y. Kim, S. Hwang, and C. Kim, “A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process,” IEEE Trans. Circuits and Systems I: Regular Papers, vol. 60, no. 14, pp. 303-313, Feb. 2013. [18] J. Lee, K. S. Kundert, and B. Razavi, “Analysis and Modeling of Bang-bang Clock and Data Recovery Circuit,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1571-1580, Sept. 2004. [19] J. Lee and K.-C. Wu, “A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition ,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3590–3602, Dec. 2009 [20] K.-C. Wu and J. Lee , “A 2 x 25Gb/s Receiver with 2:5 DMUX for 100Gb/s Ethernet,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2421–2432, Nov. 2010 [21] H. Pan, M. Valliappan, W. Zhang, K. Vakilian, S. –H. Lee, H. Hatamkhani, M. Caresosa, K. Khanoyan, H. Tong, D. Tran, A. Brewster and I. Fujimori, “A Digital Wideband CDR with 15.6kppm Frequency Tracking at 8Gb/s in 40nm CMOS,' ” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 442-444, 2011. [22] J.-W. Jung and B. Razavi, “A 25-Gb/s 5-mW CMOS CDR/Deserializer,” IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 684–697, Mar. 2013 [23] C. Kromer, G. Sialm, C. Menolfi, M. Schmatz, F. Ellinger, and H. Jackel, “A 25 Gb/s CDR in 90 nm CMOS for high-density interconnects,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2921–2929, Dec. 2006. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/56370 | - |
| dc.description.abstract | 時脈資料回復電路在有線通訊系統中扮演一個重要的角色，是一位於接收端的重要子電路，它能夠將經過長距離傳輸後具有雜訊和抖動的資料回復成乾淨的資料以利下一級電路使用。在電路架構實踐上有許多選擇，如以鎖相迴路為基礎的系統、以相位內插器為基礎的系統及以超頻取樣為基礎的系統等。
在本論文所提出一25-Gb/s具高頻率誤差容忍度之雙迴圈時脈資料回復電路。此電路裡面包含了兩個路徑，其中之一是比例路徑，另外一個是積分路徑。比例路徑和傳統以相位內插器為基礎的系統一致，可以對及時的抖動迅速產生反應。積分路徑則是透過長期累積時脈和資料的相對關係，從而萃取出資料的頻率資訊，透過除小數鎖相迴路來改變回復時脈的頻率，進而達到擴大資料率誤差容忍度的目的。 量測的結果，在0.9伏特電源供應下消耗152毫瓦，在鎖相迴路鎖定的情況下，相位雜訊在頻率偏差10 MHz為的地方為-100 dBc/Hz。調整頻率震盪器的電容陣列的情況下，鎖相迴路的鎖定範圍可以將頻率震盪器鎖定在23.7 GHz至27.3 GHz。 | zh_TW |
| dc.description.abstract | Clock and data recovery (CDR) circuit plays an important role in wireline communication, which can recover data with less jitter and filter channel interference. There’re a few common structures in CDR, phase-locked loop base CDR, phase interpolator based CDR and oversampling CDR.
The thesis proposed a 25-Gb/s dual-loop CDR circuit with enhanced data rate deviation tolerance. The proposed CDR circuit contains two feedback paths, one is proportional path, another one is integral path. Proportional path is identical to the traditional phase interpolator based CDR, which is capable of tracking to instant jitter quickly. The integral path is realized by long term accumulation of the information between clock data, which can extract the frequency information of data, and change the nominal VCO oscillation frequency by adjusting the fractional N phase-locked loop. These two paths together improve the data rate deviation tolerance of CDR. The measurement results show that the circuit consumes 152 mW under 0.9 V VDD supply. VCO’s phase noise is -100 dBc/Hz at 100-MHz. The phase-locked loop can lock VCO’s oscillation frequency from 23.7 GHz to 27.3 GHz. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T05:25:29Z (GMT). No. of bitstreams: 1 ntu-103-R00943002-1.pdf: 1667465 bytes, checksum: 78d466c6ee0d5ee38ee6e2ab9091775e (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Introduction to Optical Communication 1 1.2 Introduction to Clock and Data Recovery Circuit 2 1.3 Thesis Overview 3 Chapter 2 Basics of Clock and Data Recovery Circuits 5 2.1 Basics of a CDR Circuit 5 2.2 Frequency Detection 6 2.3 Phase Detection 7 2.3.1 Hogge Phase Detector 7 2.3.2 Alexander Phase Detector 8 2.3.3 Comparison 10 2.4 Jitter in CDR Circuits 10 2.4.1 Jitter Transfer Function 12 2.4.2 Jitter Peaking 12 2.4.3 Jitter Generation 13 2.4.4 Jitter Tolerance 14 2.5 Architectures of CDR Circuits 15 2.5.1 PLL-based CDR 15 2.5.2 Phase Interpolator Based CDR 16 2.5.3 Blind Oversampling CDR 17 Chapter 3 A 25-Gb/s Dual-Loop Clock and Data Recovery Circuit with Increased Data Rate Tolerance in 40nm Process 19 3.1 Introduction 19 3.2 System Architecture 20 3.3 Proportional Path 23 3.4 Integral Path 25 3.5 Behavior Simulation 27 Chapter 4 Implementation of a 25-Gb/s Dual-Loop Clock and Data Recovery Circuit 33 4.1 Introduction 33 4.2 Voltage Controlled Oscillator Design 34 4.3 High-Speed Divider 36 4.4 Phase-lock Loop Design 36 4.5 Half Rate Sampler 39 4.6 Phase Interpolator 40 4.7 CDR 43 Chapter 5 Measurement Result 45 5.1 Layout and Chip Photo 45 5.2 Measurement setting 45 5.3 Printed Circuit Boards Design 46 5.4 Integer N PLL Measurement Result 46 Chapter 6 Conclusions and Future Works 53 6.1 Conclusions 53 6.2 Future Works 53 Appendix 55 References 59 | |
| dc.language.iso | en | |
| dc.subject | 鎖相迴路 | zh_TW |
| dc.subject | 比例路徑 | zh_TW |
| dc.subject | 積分路徑 | zh_TW |
| dc.subject | 雙迴圈時脈資料回復電路 | zh_TW |
| dc.subject | 三角積分調變器 | zh_TW |
| dc.subject | 相位內插器 | zh_TW |
| dc.subject | Dual-loop Clock and Data Recovery Circuit | en |
| dc.subject | Phase Interpolator | en |
| dc.subject | Phase-lock Loop | en |
| dc.subject | Proportional Path | en |
| dc.subject | Integral Path | en |
| dc.subject | Delta-sigma Modulator | en |
| dc.title | 應用於兩百五十億位元具高度資料率誤差容忍度之雙迴圈時脈回復電路 | zh_TW |
| dc.title | A 25-Gbps Dual-Loop Clock and Data Recovery Circuit with Enhanced Data Rate Deviation Tolerance | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 102-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林永裕,曾英哲 | |
| dc.subject.keyword | 雙迴圈時脈資料回復電路,相位內插器,鎖相迴路,比例路徑,積分路徑,三角積分調變器, | zh_TW |
| dc.subject.keyword | Dual-loop Clock and Data Recovery Circuit,Phase Interpolator,Phase-lock Loop,Proportional Path,Integral Path,Delta-sigma Modulator, | en |
| dc.relation.page | 62 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2014-08-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-103-1.pdf 未授權公開取用 | 1.63 MB | Adobe PDF |
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