Please use this identifier to cite or link to this item:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/56254
Title: | 高速低功率的逐漸趨近式類比至數位轉換器設計 Design of High-Speed Energy-Efficient Successive-Approximation Register Analog-to-Digital Converters |
Authors: | Ting-Kai Chang 張廷愷 |
Advisor: | 陳中平(Chung-Ping Chen) |
Keyword: | 高速,低功率,逐漸趨近式,類比至數位轉換器, high speed,low power,SAR,ADC, |
Publication Year : | 2014 |
Degree: | 碩士 |
Abstract: | 本論文中提出了兩種實現高速低功率逐漸趨近式類比數位轉換器的技術,並且透過實際的晶片下線與實際量測驗證,證實所提出的電路設計技術可以有效的提升電路的操作速度以及降低整體電路的功率消耗。所提出的電路設計技術以及晶片實作成果簡述如下:
第一個技術為使用電荷分享來實現的管線式架構逐漸趨近式類比至數位轉換器,本架構使用被動元件電容來進行兩級訊號的傳遞,避免了運算放大器的使用,因此整體電路的功率消耗將大幅度的減少。本次設計使用台積電90奈米製程製作,實現一顆9位元,每秒1億次取樣的逐漸趨近式類比至數位轉換器。量測結果在輸入頻率為1M時,當操作頻率分別為10MS/s、20MS/s、50MS/s以及100MS/s時,其ENOB分別為7.33位元、7.27位元、6.92位元以及6.57位元。同時在100MS/s的操作頻率且1伏特的操作電壓時,其功率消耗為2.2毫瓦,FoM為231fJ/conversion-step。 第二個技術為多使用一組共模電壓來當作參考電壓以減少電容陣列的整體面積,同時利用電容電流落後於電壓的特性,在切換上作了一些改變,使的在第二位元切換時的電壓值不需要經由重新分布,即可到達目標的電壓值。藉由此方法,除了可以將電容陣列減少50%,同時還可以大幅降低第二位元的穩定時間。本次設計同樣使用台積電90奈米製程製作,實現一顆10位元,每秒1億次取樣的逐漸趨近式類比至數位轉換器。量測結果在輸入頻率為1M時,當操作頻率分別為10MS/s、50MS/s以及100MS/s時,其ENOB分別為7.42位元、7.57位元以及7.32位元。同時在100MS/s的操作頻率且1伏特的操作電壓時,其功率消耗為1.6毫瓦,FoM為100fJ/conversion-step。 This dissertation proposes two circuit design techniques for high-speed energy-efficient successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-and-concept prototypes, the proposed techniques are able ti improve the operating speed and decrease total circuit power consumption. The proposed techniques and chip measurement results are sketched as follows: The first technique is using charge-sharing method to achieve a Pipelined SAR ADC, this architecture using passive components capacitors for second stage sampling without using OP amplifiers, so the power consumption can be decreased greatly. A 9-bit 100MS/s SAR ADC with proposed method is implemented in TSMC 90nm 1P9M CMOS technology. As for measurement results, 1MHz input sinusoidal signal is fed into the ADC, when the operating frequency at 10MS/s, 20MS/s, 50MS/s and 100MS/s, the ENOB of ADC are 7.33 bits, 7.27 bits, 6.92 bits and 6.57 bits. The ADC consumes 2.2mW from a 1-V supply when the operating frequency at 100MS/s, the resulting figure of merit (FOM) is 231fJ/conversion-step. The second technique is adding a for reference to decrease the area of capacitor array, also we using the nature of capacitor that current will lagging the voltage, we make some change at switching, so we can achieve the target voltage without charge redistribution, we call this method “voltage-jumping” method. By using this method, we can not only decrease the capacitor array area by 50%, but also reduce the settling time of second bit. A 10-bit 100MS/s SAR ADC with proposed method is implemented in TSMC 90nm 1P9M CMOS technology. As for measurement results, 1MHz input sinusoidal signal is fed into the ADC, when the operating frequency at 10MS/s, 50MS/s and 100MS/s, the ENOB of ADC are 7.42 bits, 7.57 bits and 7.32 bits. The ADC consumes 1.6mW from a 1-V supply when the operating frequency at 100MS/s, the resulting figure of merit (FOM) is 100fJ/conversion-step. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/56254 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電子工程學研究所 |
Files in This Item:
File | Size | Format | |
---|---|---|---|
ntu-103-1.pdf Restricted Access | 5.2 MB | Adobe PDF |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.