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標題: | 一個十二位元每秒取樣五千萬次的管線式逐漸趨近式類比數位轉換器 A 12-bits 50MS/s Pipelined-SAR ADC in 0.18μm CMOS Technology |
作者: | Wei-Jin Lu 陸為仁 |
指導教授: | 陳中平(Chung-Ping Chen) |
關鍵字: | 十二位元,管線式,逐漸趨近式,類比數位轉換器, pipelined-SAR,ADC,180nm, |
出版年 : | 2014 |
學位: | 碩士 |
摘要: | 近年來,高解析度中速低耗能的類比數位轉換器已廣泛使用在行動通訊
裝置中,本論文提出一個應用於此的兩級管線式的逐漸趨近式類比數位轉換器電路,並以實際的晶片下線與量測作驗證。其電路設計技術與實作成果簡述如下: 傳統的兩級管線式逐漸趨近式類比數位轉換器,使用half gain及half reference的技巧,降低運算放大器的設計複雜度及功耗,並因較少的PAD數目,及相較於傳統管線式或逐漸趨近式的類比數位轉換器大幅縮減的晶片面積,而有非常低成本的實用價值。但因製程偏移的設計考量,單位電容值並沒有相對減小,本論文在第一級的電容陣列採用TSMC 0.18微米製程提供的最小MIM Cap,搭配改良式的電容陣列佈局,可抑制邊緣效應造成的影響,進而提升匹配精準度,第二級的電容陣列則採用單位電容值更小的MOM Cap,降低運算放大器及電容陣列切換時的功耗;在兩級各別的電容切換機制,本論文均採取改良式的單調切換方式,可減少電容切換時的功耗,同時控制比較器輸入端訊號共模電壓的動態偏移量;此外,在電路內部產生非重疊時脈及可外部調控的取樣時間和非同步的時脈控制,不僅可以避免使用數倍於取樣速度的高頻時脈訊號,在量測時亦可減緩取樣時因磅線寄生電感造成的電路效能降低。 本論文在0.18微米互補式金氧半電晶體製程下,實現一個十二位元,每秒五千萬次取樣的兩級管線式的逐漸趨近式類比數位轉換器。在1.8伏特的電壓下,輸入電壓為峰對峰值2.4伏特,其功率消耗為5.4毫瓦,有效位元為7.41bits,等效的FOM為639.44fJ/conversion-step。 Recently, high resolution and low power analog-to-digital converters (ADCs) have been widely utilized in mobile communication devices. In this thesis, a two-stage pipelined-SAR ADC is proposed. The conventional two-stage Pipelined-SAR ADC uses half-gain and half reference to alleviate the operational amplifier (OP-amp) design complexity and reduce the power consumption. Because of fewer PADs, we significantly reduce the chip area compared to both traditional pipelined ADC and SAR ADC. Because of the process variation considerations, the unit capacitance should not be reduced. Therefore, we use the smallest MIM cap (about 20fF) provided from TSMC 0.18μm CMOS technology the first-stage capacitor array. The edge effect is suppressed to improve the matching accuracy by a modified high spurious-free dynamic range (SFDR) common centroid symmetry capacitor array layout. In additional, we use MOM cap in the second-stage capacitor array for smaller capacitance (about 2.5fF) to reduce the power consumption of OP-amp and switching energy of capacitor array. In each capacitor switching strategy, the modified monotonic switching procedure is adopted to reduce the average switching energy and alleviate the signal-dependent dynamic offset caused by the variation of input common-mode voltage. Besides, we generate two-phase non-overlapping clock signal and asynchronous control signal with external tunable sampling width, to make clock frequency lower than sampling rate and alleviate the performance degradation induced by bondwire parasitic inductance in sampling phase. The 12-bit, 50-MS/s two-stage Pipelined-SAR ADC implemented in a 0.18-μm 1P6M CMOS technology. Under 1.8-V supply voltage, the ADC consumes 5.4 mW with 2.4Vp-p input range. The peak ENOB and SFDR is 7.41 bits and 56.93 dB. The FOM is 639.44fJ/conversion-step. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/56121 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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