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Title: | p型與n型超薄金氧半電容元件電流穿隧行為之比較與探討 Investigation of Current Tunneling Behavior for p- and n-type MOS Capacitors with Ultra-thin Oxides |
Authors: | Han-Wei Lu 呂涵薇 |
Advisor: | 胡振國 |
Keyword: | 電流穿隧行為,反曲點,面積/周長相依性,金氧半電容元件, current tunneling behavior,kinked effect,area/perimeter dependencies,MOS capacitors, |
Publication Year : | 2014 |
Degree: | 博士 |
Abstract: | 本篇論文主要探討p型與n型超薄閘極氧化層金氧半電容元件於累積區和深空乏區的電流穿隧行為。在論文的第二章中,我們發現,當p型矽基板的金氧半電容元件位於累積區時,元件的電流特性曲線有一個明顯的反曲點,我們合理的推斷此反曲點應該是跟位於閘極氧化層兩邊的金屬-半導體不對稱結構有關。經由理論公式搭配由實驗結果取得的數據來模擬得到了一個結論,反曲點就是元件從平能帶電壓慢慢進入累積區,矽基板的能帶彎曲到不能再彎曲,外加偏壓壓降開始幾乎只降在氧化層上的那個點,反曲點和氧化層厚度、介面特性和氧化層中的電荷量強烈相關。基於這個p型矽基板的金氧半電容元件之電流位於累積區會有一反曲點的原生特性,我們將其應用在超薄閘極氧化層厚度的萃取。而我們在n型矽基板的金氧半電容元件的順向偏壓區並沒有看到反曲點的現象,這是因為當元件偏壓在順向偏壓時,n型矽基板金氧半電容元件的能帶圖的方向都是一致的,都是在累積區。
在論文的第三章中,我們發現,p型與n型金氧半電容元件的電流特性曲線對閘極氧化層厚度的相依性是截然不同的,有趣的面積和周長相依特性在本章節中被提出。對於p型矽基板的金氧半電容元件而言,金屬和矽基板間的蕭基位障是不能被忽略的,但對於n型基板的金氧半電容元件而言,蕭基位障的影響較小。此外,邊際電場效應會使得p型基板的金氧半電容元件具有邊緣相關的電流特性,而n型基板的金氧半電容元件的電流則是與面積相關。 在論文的第四章中,我們設計三個不同厚度的正面鋁金屬閘極p型矽基板的金氧半電容元件來進一步研究元件的邊際不均勻現象。從電容和電流的特性曲線中發現,超薄的(<4奈米)鋁金屬閘極元件的表現和較厚的鋁金屬閘極不太一樣,主要是因為元件會在位於超薄的鋁金屬閘極下方先進入深空乏區域,而元件邊際則還是在反轉區域,此時元件邊際可以提供電子去補充元件中心以維持電荷平衡,使得超薄鋁金屬閘極元件的空乏區電流會比較厚鋁金屬閘極元件增大許多,也就是說,邊際電場效應會加強元件的邊際電荷收集效率。 In this thesis, the current tunneling behaviors of MOS(p) and MOS(n) capacitors with ultra-thin SiO2 dielectric were explored under both accumulation and deep depletion modes. In Chapter 2, it is found that there is a clear “kinked point” in every I-V curve of MOS(p) capacitor under accumulation mode. It is reasonable to suspect that it is related to the unsymmetrical structure between the metal aluminum and substrate Si. By the theoretical simulation with the experimental results, it is concluded that the kinked voltage VG@|JG|’min is inferred to VG@EFS=EV but not VFB and are strongly dependent on oxide thickness, Dit, and Qeff/q. Based on the intrinsic kinked characteristic of I-V curve under accumulation region in MOS(p) devices, a further application to extract ultra-thin oxide thickness will be carried out. On the other hand, this kinked phenomenon does not appear in the forward positive bias J-V curve of MOS(n) capacitors. That is because there is no change of the direction of the band bending for MOS(n) capacitors in the forward bias. In Chapter 3, it is found that the dependencies of I-V curves on gate oxide thickness for MOS(p) and MOS(n) capacitors are definitely different. Interesting area- and perimeter-dependent mechanisms of gate current are observed. The main issue is the Schottky barrier between metal and the silicon substrate could not be ignored for MOS(p) capacitors but would be less pronounced for MOS(n) capacitors. In addition, the effect of fringing field would further enhance the edge-dependent current conduction of MOS(p) capacitors. For MOS(n) capacitors, the current are area-dependent. In Chapter 4, to study this lateral non-uniformity phenomenon, three different thicknesses of top aluminum gate are intentionally designed to MOS(p) capacitors. According to C-V and I-V measurements carried out in the dark, it is found that the device with thin (< 4 nm) top Al-gate will result in entirely different electrical characteristics compared with the device with thick top Al-gate. It shows that the area beneath the probe enters deep depletion region earlier. And other areas which are still in inversion region will provide electrons to the gate center and therefore induce extra current in deep depletion region. That is, there is enhanced edge charge collection efficiency in inversion due to edge fringing field effect. Through this study, a thorough understanding of the basic characteristics of MOS(p) and MOS(n) capacitors could be achieved. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/55467 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電子工程學研究所 |
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