暫存器轉換層級設計之除錯與驗證藉由設計知識之正規語意模型與推論

Abstract

暫存器轉換層級設計的除錯與驗證一直是個很有挑戰的問題，傳統的除錯方式常使用將多工器插入設計中以找出可能發生錯誤的位置。然而，因為設計的複雜度以及工程師本身對設計知識的了解，大部分工程師選擇藉由觀察波型圖找出可能的錯誤而非使用自動診斷及除錯工具。若能在除錯及驗證上整合人類的使用行為及知識將會是一個值得研究的方向。 我們提出一個新方法以及建構一個系統以對暫存器轉換層級進行除錯，就像平常工程師所習慣的藉由引進設計知識的正規語意模型及推論來除錯。透過程式語言以及設計知識的語意我們可以容易的找出可能發生錯誤的位置，此外我們也可以使用語意模型及設計知識將確認及監視自動地寫入設計中，最後，我們得出這個系統的優缺點，以及未來可行的研究方向來改進此系統。

RTL (Register Transaction Level) design debugging and verification is always a challenging problem. Traditionally, the research of debugging used to insert MUX (Multiplexer) into design to find the bugs. However, because of the complexity and designer’s design knowledge of RTL design, most engineers used to use waveform tools (e.g. Verdi) with design knowledge to debug rather than using automatic debugging tool. Combining the human’s behavior and knowledge on debugging and verification is a good perspective to research. We proposes a new approach and builds a system to debug RTL design by introducing formal semantic model and inference with design knowledge just like what designers used to do. With semantic of RTL code, design knowledge, we can easily infer what may cause these bugs. Also, we can use this semantic model and design knowledge to automatically write assertion and monitor into design. Finally, we point out the strengths and weaknesses of this approach, and possibilities on future research to improve our system.