一個每秒三十億位元串列數位介面等化器

Abstract

隨著寬頻通訊快速發展，可接收到更高速度的資料就變成一個重要的考量，不同的串列數位介面標準都使用同軸電纜當作傳遞介質，當頻率增加電纜損失會變大而更長的電纜也會受到嚴重的損失，串列數位介面資料中會包含來由是不歸零制編碼後連續相同資料型式，此編碼會因為太長的零或一字串，導致基準線會掉到共模訊號，稱之為基準線飄移。所以一個以90奈米CMOS製程實現每秒三十億位元串列數位介面等化器，去提供補償電纜在高頻的損失和低頻基準線偏移的補償，使得串列數位介面訊號得以傳送。 使用五十米電纜線，測得每秒十五億位元等化後輸出最小峰對峰值抖動為158.57微微秒(0.24單位區間)和每秒三十億位元等化後輸出最小峰對峰值抖動為274.13微微秒(0.82單位區間)；使用一百米電纜線，測得每秒十五億位元等化後輸出最小峰對峰值抖動為498.01微微秒(0.75單位區間)。在我們量測結果中，所有等化器輸出眼圖都比電纜輸出失真眼圖還要好。

With the rapid development of broadband data communication, receiving at high data rates becomes a major concern. The various Serious Digital Interface (SDI) standards all use coaxial cables for transmission media. The cable loss becomes larger when the frequency increases, and the longer cable has server insertion loss. The SDI data in Consecutive Identical Data (CID) pattern which is scrambled by NRZ format will cause the baseline wander that long strings of zeros or ones drop to the common mode. So, a 3Gb/s SDI Equalizer in 90-nm CMOS technology provides gain boosting at high frequencies to compensate the cable loss and low frequency compensation for baseline wander. The SDI signals can be correctly transmitted. By using 50 meters cable, measured min. peak-to-peak jitter of 1.5Gb/s equalized output is 158.57ps (0.24UI) and peak-to-peak jitter of 3Gb/s equalized output is 274.13ps (0.82UI). By using 100 meters cable, measured min. peak-to-peak jitter of 1.5Gb/s equalized output is 498.01ps (0.75UI). All eye diagrams of equalized output are better than distorted eyes of cable output in our measurement results.