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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/53024完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
| dc.contributor.author | Wen-Chieh Kuo | en |
| dc.contributor.author | 郭文杰 | zh_TW |
| dc.date.accessioned | 2021-06-15T16:39:51Z | - |
| dc.date.available | 2020-08-25 | |
| dc.date.copyright | 2015-08-25 | |
| dc.date.issued | 2015 | |
| dc.date.submitted | 2015-08-11 | |
| dc.identifier.citation | [1] J. Lee, “A 20-Gb/s Adaptive Equalizer in 0.13- m CMOS Technology” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2058-2066, Sep. 2006. [2] S. Agarwal, and V. S. R. Pasupureddi, “A 5-Gb/s Adaptive CTLE with Eye-Monitoring for Multi-Drop Bus Applications” IEEE MWSCAS, 2014, pp. 410-413. [3] W.-S. Kim, C.-K. Seong, and W.-Y. Choi, “A 5.4Gb/s Adaptive Equalizer Using Asynchronous-Sampling Histograms” IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 358-359. [4] H. Wang, and J. Lee, “A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 909-920, Apr. 2010. [5] S. Haykin, “Adaptive Filter Theory” Prentice Hall, 2001. [6] J. Lee, and K.-C. Wu, “A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3590-3602, Dec. 2009. [7] “Serial Digital Interface” [Online]. Available: http://en.wikipedia.org/wiki/Serial_digital_interface. [8] “TI Application Report ZHCA485” [Online]. Available: http://www.ti.com.cn/cn/lit/an/zhca485/zhca485.pdf. [9] “Understanding the blocking capacitor effect on the HD/SD pathological signals” [Online]. Available: http://www.hostgeni.net/host-info/brioconcept.com. [10] W.-Y. Lee, K.-D. Hwang, and L.-S. Kim, “A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme” IEEE Trans. Circuits Syst. I, vol. 59, no. 12, pp. 2858-2866, Dec. 2012. [11] J.-S. Choi, M.-S. Hwang, and D.-K. Jeong, “A 0.18- m CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method” IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 419-425, Mar. 2004. [12] H. Chen, X. Li, C. Xu, Q. Gao, and S. Qin, “Baseline Wander Compensation Circuit for 100/1000Base-TX Application” IEEE ICSICT, 2006, pp. 2000-2002. [13] K.-H. Cheng, Y.-C. Tsai, Y.-H. Wu, and Y.-F. Lin, “A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications” IEEE Trans. Circuits Syst. II, vol. 57, no. 5, pp. 324-328, May. 2010. [14] “SD-SDI and HD-SDI Checkfield Testing on Hotlink IITM Transceivers for SMPTE Pathological Condition” [Online]. Available: http://www.cypress.com/?docID=47752. [15] “LMH0344 3Gbps HD/SD SDI Adaptive Cable Equalizer” [Online]. Available: http://www.digchip.com/datasheets/download_datasheet.php?id=1108029 part-number=LMH0344. [16] H.-Y. Joo, and L.-S. Kim, “A Data-Pattern-Tolerant Adaptive Equalizer Using the Spectrum Balancing Method” IEEE Trans. Circuits Syst. II, vol. 57, no. 3, pp. 228-232, Mar. 2010. [17] J. Everitt, J. F. Parker, P. Hurst, D. Nack, and K. R. Konda, “A CMOS Transceiver for 10-Mb/s and 100-Mb/s Ethernet” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2169-2177, Dec. 1998. [18] Y.-B. Luo, P. Chen, Q.-T. Chen, C.-Y. Wang, C.-H. Chang, S.-J. Fu, C.-M. Chen, and H.-S. Li, “A 250Mb/s-to-3.4Gb/s HDMI Receiver with Adaptive Loop Updating Frequencies and an Adaptive Equalizer” IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 190-191,191a. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/53024 | - |
| dc.description.abstract | 隨著寬頻通訊快速發展，可接收到更高速度的資料就變成一個重要的考量，不同的串列數位介面標準都使用同軸電纜當作傳遞介質，當頻率增加電纜損失會變大而更長的電纜也會受到嚴重的損失，串列數位介面資料中會包含來由是不歸零制編碼後連續相同資料型式，此編碼會因為太長的零或一字串，導致基準線會掉到共模訊號，稱之為基準線飄移。所以一個以90奈米CMOS製程實現每秒三十億位元串列數位介面等化器，去提供補償電纜在高頻的損失和低頻基準線偏移的補償，使得串列數位介面訊號得以傳送。 使用五十米電纜線，測得每秒十五億位元等化後輸出最小峰對峰值抖動為158.57微微秒(0.24單位區間)和每秒三十億位元等化後輸出最小峰對峰值抖動為274.13微微秒(0.82單位區間)；使用一百米電纜線，測得每秒十五億位元等化後輸出最小峰對峰值抖動為498.01微微秒(0.75單位區間)。在我們量測結果中，所有等化器輸出眼圖都比電纜輸出失真眼圖還要好。 | zh_TW |
| dc.description.abstract | With the rapid development of broadband data communication, receiving at high data rates becomes a major concern. The various Serious Digital Interface (SDI) standards all use coaxial cables for transmission media. The cable loss becomes larger when the frequency increases, and the longer cable has server insertion loss. The SDI data in Consecutive Identical Data (CID) pattern which is scrambled by NRZ format will cause the baseline wander that long strings of zeros or ones drop to the common mode. So, a 3Gb/s SDI Equalizer in 90-nm CMOS technology provides gain boosting at high frequencies to compensate the cable loss and low frequency compensation for baseline wander. The SDI signals can be correctly transmitted. By using 50 meters cable, measured min. peak-to-peak jitter of 1.5Gb/s equalized output is 158.57ps (0.24UI) and peak-to-peak jitter of 3Gb/s equalized output is 274.13ps (0.82UI). By using 100 meters cable, measured min. peak-to-peak jitter of 1.5Gb/s equalized output is 498.01ps (0.75UI). All eye diagrams of equalized output are better than distorted eyes of cable output in our measurement results. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T16:39:51Z (GMT). No. of bitstreams: 1 ntu-104-R01943165-1.pdf: 5715028 bytes, checksum: 91a3f63e94597f1a452144ced97bc16a (MD5) Previous issue date: 2015 | en |
| dc.description.tableofcontents | 致謝…………………………………………………………………………………...III 摘要…………………………………………………………………………………..IV Abstract....... V Contents…... VI List of Figures IX List of Tables XV Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 1 Chapter 2 Fundamentals of Wireline Receiver 2 2.1 Equalizer 2 2.1.1 Continuous Time Linear Equalizer 2 2.1.2 Decision Feedback Equalizer 5 2.2 Clock and Data Recovery 8 Chapter 3 Equalizer in Serial Digital Interface 9 3.1 Introduction 9 3.2 Electrical Specifications 10 3.3 Cable loss 11 3.3.1 Cable model 11 3.3.2 Return loss 11 3.3.3 Insertion loss 13 3.4 Pathological pattern 15 3.4.1 Consecutive Identical Data 15 3.4.1.1 Baseline wander 16 3.5 SDI Transmitter 17 3.5.1 Transmitter model 17 3.6 Summary 18 Chapter 4 Equalizer Architecture and Circuit Implementation 19 4.1 Block Diagram of Equalizer 19 4.2 Circuit Implementation 20 4.2.1 Equalizing Filter 20 4.2.2 VGA (Variable Gain Amplifier) 22 4.2.3 Slicer 23 4.2.4 DC restore 24 4.2.4.1 Adder 24 4.2.4.2 Low pass filter 27 4.3 Simulation Results 28 4.3.1 Behavior Simulation 28 4.3.2 Transistor Level Simulation 30 4.4 Summary 34 Chapter 5 Measurement Results 35 5.1 Measurement Setup 35 5.2 PCB Design 37 5.3 Floor Plan and Layout 40 5.4 Experimental Results 43 5.4.1 Measured eye diagrams using 50 meters cable 45 5.4.2 Measured eye diagrams using 100 meters cable 52 5.5 Summary 54 Chapter 6 Conclusions and Future Work 56 6.1 Conclusions 56 6.2 Future Work 57 Bibliography 58 | |
| dc.language.iso | en | |
| dc.title | 一個每秒三十億位元串列數位介面等化器 | zh_TW |
| dc.title | A 3Gb/s Serial Digital Interface Equalizer | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 103-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),陳怡然(Yi-Jan Chen) | |
| dc.subject.keyword | 串列數位介面,不歸零,連續相同資料,基準線偏移,等化器, | zh_TW |
| dc.subject.keyword | Serial Digital Interface,NRZ,CID,Baseline wander,Equalizer, | en |
| dc.relation.page | 60 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2015-08-11 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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