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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/51691
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor林宗賢
dc.contributor.authorMing-Yen Hoen
dc.contributor.author何明諺zh_TW
dc.date.accessioned2021-06-15T13:44:49Z-
dc.date.available2021-02-02
dc.date.copyright2016-02-02
dc.date.issued2015
dc.date.submitted2015-12-03
dc.identifier.citation[1] A. K. Kalgi, “A Gm-C based Continuous-Time Ʃ∆ modulator with a compact FIR-DAC,” Master Thesis
[2] G. Singh, “ A Gm-C Continuous-Time Sigma-Delta Modulator with Improved Linearity,” Master Thesis
[3] C.-C. Tu, “Design of Low-Power Low-Noise Analog Front-End Circuits for Biomedical Applications,' Master Thesis
[4] S.-C. Hsu, “Linearization Techniques for VCO-Based Delta-Sigma Modulator,” Master Thesis
[5] M. H. Perrott, “Oversampled ADC using VCO-Based Quantizers,” VCO-Based Tutorial
[6] N. Sarhangnejad, R. Wu, Y. Chae and K.A.A. Makinwa, “A continuous-time Sigma-Delta modulator with a Gm-C input stage, 120-dB CMRR and -87 dB THD,' in Proc. IEEE Asian Solid-State Circuits Conf., 2011, pp. 245-248
[7] G. Taylor and I. Galton, “A Mostly Digital Variable-rate Continuous-time ADCΔΣ Modulator,” in IEEE Int. Solid-State Circuits Conf. Dig.2010, pp. 298-299
[8] M. Z. Straayer and M. H. Perrott, “A 12-bit 10-MHz bandwidth, continuous time sigma-delta ADC with a 5-bit, 950-MS/S VCO-based quantizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805–814, Apr. 2008.
[9] S. Rao, B. Young, A. Elshazly, W. Yin, N. Sasidhar, and P. K. Hanumolu, “A 71dB SFDR Open Loop VCO-Based ADC Using 2-Level PWM Modulation,” Symposium on VLSI Circuits, pp. 270-271, June 2011.
[10] P. Prabha, S. J. Kim, K. Reddy, S. Rao, N. Griesert, A. Rao, G. Winter, and P. K. Hanumolu, “A Highly Digital VCO-Based ADC Architecture for current sensing applications,” IEEE J. Solid-State Circuits, vol. 50, no. 8, pp. 1785-1795, Aug. 2015.
[11] J. Kim, T.-K. Jang, Y.-G. Yoon and S. Cho, “Analysis and Design of Voltage-Control Oscillator Analog-to-Digital Converter,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 1, pp. 18-30, Jan. 2010.
[12] R. F. Yazicioglu, C. Van Hoof, and R. Puers, Biopotential Readout Circuits for Portable Acquisition Systems, Springer, 2009.
[13] M.A.P. Pertijs, and W.J. Kindt, 'A 140 dB-CMRR Current-Feedback Instrumentation Amplifier Employing Ping-Pong Auto-Zeroing and Chopping,' IEEE J. Solid-State Circuits, vol.45, No.10, pp. 2044- 2056, Oct. 2010.
[14] R. Wu, K.A.A. Makinwa and J.H. Huijsing, “A Chopper Current-Feedback Instrumentation Amplifier with a 1mHz 1/f Noise Corner and an AC-Coupled Ripple Reduction Loop,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3232 -3243, Dec. 2009.
[15] R. Wu, J.H. Huijsing and K.A.A. Makinwa, “A Current-Feedback Instrumentation Amplifier with a Gain Error Reduction Loop and 0.06% Untrimmed Gain Error,” IEEE J. Solid-State Circuits, vol. 46, no. 12, Dec. 2011.
[16] R. Wu, Y. Chae, J.H. Huijsing and K.A.A. Makinwa, “A 20-b ±40-mV Range Read-Out IC With 50-nV Offset and 0.04% Gain Error for Bridge Transducers” IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2152-2163, Sept. 2012.
[17] Q. Fan, F. Sebastiano, J.H. Huijsing and K.A.A. Makinwa, “A 1.8µW 1µV-Offset Capacitively-Coupled Chopper Instrumentation Amplifier in 65nm CMOS,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1534 - 1543, July 2011.
[18] Q. Fan, J.H. Huijsing and K.A.A. Makinwa, “A Capacitively Coupled Chopper Instrumentation Amplifier With a ±30V Common-Mode Range 160dB CMRR and 5μV Offset,” Digest ISSCC, pp. 374 – 376, Feb. 2012.
[19] A. Leuciuc, “A linear MOS tranconductor using source degeneration and adaptive biasing,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 48, no. 10, pp. 937-943, Oct. 2001.
[20] J. Bergs, “Design a VCO based ADC in a 180 nm CMOS Process for use in Positron Emission Tomography,” Master Thesis
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/51691-
dc.description.abstract橋式感測器廣泛運用在許多量測,像是溫度感測、壓力感測。傳統生醫訊號感測器需要許多電路來實現,包括低雜訊放大器、反鋸齒濾波器和非連續的類比數位轉換器。這些系統包含需多高增益的開放式電路,遠高於用一個回授電路所需要的增益要求。這會造成需要更多的能量消耗,以及增加生醫感測讀取系統上類比電路設計的複雜度。
這裡所提出來的架構是一個Gm-C 為基礎連續時間的三角積分器且採用震盪器基礎的量化器。這個架構取代了傳統架構,因為此架構具有天生的反鋸齒濾波器和天生的動態原件匹配。並且達到高輸入阻抗、低功率消耗和高解析度。然而,運用在準確的橋式電路感測器會受限於非線性的輸入端。此外震盪器的非線性轉移函數也會嚴重的限制整個系統的效能。在我們的電路利用一個相同非線性的電路做負回授。這樣可以消除偶數次的頻調,且可以壓抑輸入端所造成的非線性。我們採用係數調整技巧讓震盪器的輸入訊號的振幅變小,跟之前的震盪器基礎之類比數位轉換器相比,是一個最簡單的方式來改善震盪器的線性度。
本案是用台積電90奈米互補式金屬半製程來做設計和實現。此系統頻寬為1 kHz,取樣頻率為1 MHz,在1 V的操作電壓下,功率消耗為586 uW。
zh_TW
dc.description.abstractBridge sensors have been widely applied to accurate measurement of physical quantities such as temperature, pressure, strain or altitude. In order to meet these requirements, conventional biomedical sensor readout systems use multiple stages, typically including a low noise amplifier, an anti-aliasing filter and a discrete-time (DT) delta-sigma modulator (∆ƩM). As a result, such a system involves several high-gain loops with total open-loop gain, far exceeding the required gain of a closed loop. Hence, it can lead to more power dissipation and increase the complexity in the design of analog biomedical sensor readout system.
The architecture proposed in this study is a Gm-C-based continuous-time (CT) delta-sigma modulator (∆ƩM) with a VCO-based quantizer. The architecture replaces original sensor readout system and draws a lot of attention due to its inherent anti-alias filtering, inherent DEM for DAC, producing high input impedance, low power consumption and high resolution. However, the usage in precision applications such as a bridge sensor readout system is limited by the non-linearity input stage. Additionally, the nonlinear transfer function of VCO also severely limits the total system performance. Hence, the following method is taken to solve these issues. In our work, we employ an identical nonlinear element in the negative feedback path. It can cancel the even order harmonic tones and suppress the nonlinearity of input. We use parameter scaling technique to reduce VCO input swing. Compared with previous VCO-based ADC, it is the simplest way to improve VCO non-linearity.
The proposed work is designed and implemented in TSMC 90-nm CMOS technology. The system bandwidth is designed at 1 kHz with 1MHz sampling frequency. It consumes 586 uW from a 1V supply.
en
dc.description.provenanceMade available in DSpace on 2021-06-15T13:44:49Z (GMT). No. of bitstreams: 1
ntu-104-R00943166-1.pdf: 7212500 bytes, checksum: 863dc296e517c49c6406b410919d230c (MD5)
Previous issue date: 2015
en
dc.description.tableofcontentsChapter 1 Introduction 1
1.1 Motivation 1
1.2 Target Specifications 3
1.3 Dissertation Overview 3
Chapter 2 Theory and Background 5
2.1 Introduction 5
2.2 Bridge Sensor 5
2.3 Instrumentation Amplifier 7
2.3.1 Three-OPAMP Instrumentation Amplifier 7
2.3.2 Current-Feedback Instrumentation Amplifier 8
2.3.3 Capacitively-Coupled Instrumentation Amplifier 10
2.4 Delta-Sigma ADC 11
Chapter 3 Analog-to-Digital Converter with VCO-Based Quantizer 13
3.1 Introduction 13
3.2 Architecture 14
3.3 First Order Noise Shaping 16
3.4 SNR in VCO-Based ADC 17
3.5 VCO Signal Process Properties 18
3.6 Non-Ideal Effects 19
3.7 Prior Work 21
3.7.1 Digital Background Calibration 22
3.7.2 Pulse Width Modulation (PWM) 23
3.7.3 Swing Reduction 24
3.8 Proposed Concept 26
Chapter 4 VCO-Based Continuous-Time Delta-Sigma ADC 33
4.1 Overview of Proposed Architecture 33
4.2 The Challenges to Implement Proposed Architecture 35
4.2.1 The Transistor-Level Techniques to Linearize the Transconductance 35
4.2.2 Nonlinearity Cancellation Through Negative Feedback 42
4.3 Proposed CTDSM Architecture 43
4.3.1 The Architecture with 1-bit ADC and DAC 44
4.3.2 The architecture with Multi-bit ADC and DAC 45
4.3.3 The Architecture with 1-bit ADC and DAC and Filter 45
4.4 Chopper Technique 47
4.5 Proposed System with VCO-Based Quantizer 48
4.5.1 Summary 48
4.5.2 Stability 50
4.6 Simulation Results 51
Chapter 5 Implementation and Results 54
5.1 Transistor Level Design and Simulation Results 54
5.1.1 First Stage Integrator 54
5.1.2 VCO-Based Quantizer 61
5.1.3 DAC 63
5.1.4 Power Consumption 64
5.2 Layout 65
5.3 Measurement Results 66
5.3.1 Test Setup 66
5.3.2 PCB setup 67
Chapter 6 Conclusions and Future Works 71
6.1 Conclusions 71
6.2 Future Work 71
References 73
dc.language.isoen
dc.subject三角積分調變器zh_TW
dc.subject低功率zh_TW
dc.subject壓控震盪器基礎之類比數位轉換器zh_TW
dc.subject橋式感測器之應用zh_TW
dc.subjectVCO-based ADCen
dc.subjectDelta-Sigma Modulatoren
dc.subjectBridge Sensor Applicationen
dc.subjectLow Poweren
dc.title應用於橋式電路感測系統之振盪器基礎的連續時間三角積分器zh_TW
dc.titleVCO-Based Continuous-Time Delta-Sigma ADC for Bridge Sensor Applicationsen
dc.typeThesis
dc.date.schoolyear104-1
dc.description.degree碩士
dc.contributor.oralexamcommittee曾英哲,李泰成,吳宗佑
dc.subject.keyword低功率,壓控震盪器基礎之類比數位轉換器,橋式感測器之應用,三角積分調變器,zh_TW
dc.subject.keywordLow Power,VCO-based ADC,Bridge Sensor Application,Delta-Sigma Modulator,en
dc.relation.page75
dc.rights.note有償授權
dc.date.accepted2015-12-03
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電子工程學研究所zh_TW
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