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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Yun-Xiang Hong | en |
dc.contributor.author | 洪韻翔 | zh_TW |
dc.date.accessioned | 2021-06-15T13:43:12Z | - |
dc.date.available | 2025-12-21 | |
dc.date.copyright | 2016-02-15 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-12-22 | |
dc.identifier.citation | [1] Y. Ban, K. Lucas, and D. Pan, 'Flexible 2D layout decomposition framework for spacer-type double pattering lithography,' in Proceedings of ACM/IEEE Design Automation Conference (DAC), pp. 789-794, 2011.
[2] H.-Y. Chen, M.-F. Chiang, and Y.-W. Chang, 'Novel full-chip gridless routing considering double-via insertion,' in Proceedings of ACM/IEEE Design Automation Conference (DAC), pp. 755-760, 2006. [3] H.-Y. Chen, M.-F. Chiang, Y.-W. Chang, L. Chen, and B. Han, 'Full-chip routing considering double-via insertion,' in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 5, pp. 844-857, 2008. [4] M. Cho, Y. Ban, and D. Z. Pan, 'Double patterning technology friendly detailed routing,' in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 506-511, 2008. [5] Y. Du, Q. Ma, H. Song, J. Shiely, G. Luk-Pat, A. Miloslavsky, and M. D. F. Wong, 'Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography,' in Proceedings of ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2013. [6] Y. Du, D. Guo, M. D. F. Wong, H. Yi, H.-S. P. Wong, H. Zhang, and Q. Ma, 'Block copolymer directed self-assembly (DSA) awrae contact layer optimization for 10 nm 1D standard cell library,' in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 186-193, 2013. [7] Y. Du, Z. Xiao, M. D. F.Wong, H. Yi, and H.-S. P.Wong, 'DSA-aware detailed routing for via layer optimization,' in Proc. SPIE, vol. 9049, pp. 904920, 2014. [8] S.-Y. Fang, 'Lithography Optimization for sub-22 Nanometer Technologies,' Graduate Institute of Electronic Engineering, National Taiwan University, 2013. [9] S.-Y. Fang, Y.-W. Chang, and W.-Y. Chen, 'A novel layout decomposition algorithm for triple patterning lithography,' in Proceedings of ACM/IEEE Design Automation Conference (DAC), pp. 1181-1186, 2012. [10] J.-R. Gao and D. Z. Pan, 'Flexible self-aligned double patterning aware detailed routing with prescribed layout planning,' in Proceedings of ACM International Symposium on Physical Design (ISPD), pp. 25-32, 2012. [11] D. Herr, 'The extensibility of optical patterning via directed self-assembly of nano-engineered imaging materials,' Future Fab International (www.futurefab.com), vol. 18, 2005. [12] A. B. Kahng, C.-H. Park, X. Xu, and H. Yao, 'Layout decomposition approaches for double patterning lithography,' in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, no. 6, pp. 939-952, 2010. [13] J. Kuang and E. F. Y. Young, 'An efficient layout decomposition approach for triple patterning lithography,' in Proceedings of ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2013. [14] Y.-Z. Lu,'Simultaneous Guiding Template Optimization and Redundant Via Insertion for Directed Self-Assembly,' Department of Electrical Engineering, National Taiwan University of Science and Technology, 2015. [15] K.-Y. Lee and T.-C. Wang, 'Post-routing redundant via insertion for yield/reliability improvement,' in Proc. IEEE/ACM Asia South Pacific Des. Autom. Conf., pp. 303-308, 2006. [16] K.-Y. Lee, C.-K. Koh, T.-C. Wang, and K.-Y. Chao, 'Optimal post-routing redundant via insertion,' in Proceedings of ACM International Symposium on Physical Design (ISPD), pp. 111-117, 2008. [17] K.-Y. Lee, C.-K. Koh, T.-C. Wang, and K.-Y. Chao, 'Fast and optimal redundant via insertion,' in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 12, pp. 2197-2208, 2008. [18] K.-Y. Lee, S.-T. Lin, and T.-C. Wang, 'Redundant via insertion with wire bending,' in Proceedings of ACM International Symposium on Physical Design (ISPD), pp. 123-130, 2008. [19] K.-Y. Lee, T.-C. Wang, C.-K. Koh, and K.-Y. Chao, 'Optimal double via insertion with on-track preference,' in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, no. 2, pp. 318-323, 2010. [20] S.-T. Lin, K.-Y. Lee, T.-C. Wang, C.-K. Koh, and K.-Y. Chao, 'Simultaneous redundant via insertion and line end extension for yield optimization,' in Proc. ASPDAC, pp. 633-638, 2011. [21] I.-J. Liu, S.-Y. Fang, and Y.-W. Chang, 'Overlay-aware detailed routing for self-aligned double patterning lithography using the cut process,' in Proceedings of ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2014. [22] Q. Ma, H. Zhang and M. D. F. Wong, 'Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology,' in Proceedings of ACM/IEEE Design Automation Conference (DAC), pp. 591-596, 2012. [23] H.-Y. Tsai, M. Guillorn, G. Doerk, J. Cheng, D. Sanders, K. Lai, C.-C. Liu and M. Colburn, 'Directed self-assembly for ever-smaller printed circuits,' SPIE newsroom http://spie.org/x93535.xml?highlight=x2402&ArticleID=x93535 0, 0 (2013) [24] Z. Xiao, Y. Du, H. Tian, M. D. F. Wong, H. Yi, and H.-S. P. Wong, 'DSA template optimization for contact layer in 1D standard cell design,' in Proc. SPIE, vol. 9049, pp. 90492J, 2014. [25] Z. Xiao, Y. Du, H. Tian, M. D. F. Wong, H. Yi, H.-S. P. Wong, and H. Zhang, 'Directed self-assembly (DSA) template pattern veri cation,' in Proceedings of ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2014. [26] H. Yi, X.-Y. Bao, J. Zhang, R. Tiberio, J. Conway, L.-E. Chang, S. Mitra, and H.-S. P. Wong, 'Contact hole patterning for random logic circuits using block copolymer directed self-assembly,' in Proc. SPIE, vol. 8323, pp. 83230W, 2012. [27] H. Yi, X.-Y. Bao, R. Tiberio, and H.-S. P. Wong, 'Design strategy of small topographical guiding templates for sub-15 nm integrated circuits contact hole patterns using block copolymer directed self-assembly,' in Proc. SPIE, vol. 8680, pp. 868010, 2013. [28] IBM ILOG CPLEX Optimizer. http://www-01.ibm.com/software/integration/optimization/cplex-optimizer/ [29] International Technology Roadmap for Semiconductors (ITRS). http://www.itrs.net/ | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/51657 | - |
dc.description.abstract | Directed self-assembly (DSA) lithography technology, which has shown its strong potential for contact/via fabrication, is the most promising candidate patterning dense layout for next generation lithography in sub-10 nm technology nodes. On the other hand, post-routing redundant via insertion process adding a redundant via adjacent to a single via has become an important semiconductor manufacturing procedure highly recommended by foundries to increase yield and circuit reliability. However, existing redundant via insertion algorithms are not suitable for DSA since they could seriously decrease via manufacturability. Although the first ILP-based algorithm for redundant via insertion considering DSA has been proposed in [14], this method suffer from high computational complexity and may not efficient enough for a large and complicated circuit design. In this work, we proposed two efficient algorithms to simultaneously optimize DSA guiding templates and redundant via insertion rate. A graph-based approach is first presented to find a near-optimal solution of DSA-aware redundant via insertion of a given layout in linear time. Then, an advanced integer linear programming (ILP)-based algorithm is proposed to find an optimal solution. Moreover, we utilized wire perturbation to further enhance the quality of DSA-aware redundant via insertion. Experimental results show that our algorithms can effectively optimize the redundant via insertion rate and improve DSA manufacturability. Compared to the first ILP-based method [14], our graph algorithm and ILP approach can achieve 40X and 2X speed-up respectively. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T13:43:12Z (GMT). No. of bitstreams: 1 ntu-104-R02943147-1.pdf: 5319637 bytes, checksum: c75f99f41bd88cba5520984ee9485749 (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | Acknowledgements iii
Abstract (Chinese) iv Abstract vi List of Tables x List of Figures xi Chapter 1. Introduction 1 1.1 Challenges for Lithography . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 DSA Lithography Technologies . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 Motivation and Contributions . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 2. Preliminaries 12 2.1 Guiding Templates for Via Fabrication . . . . . . . . . . . . . . . . . . 12 2.2 Redundant Via Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 3. Algorithms 16 3.1 An Effective Graph-Based Algorithm for Guiding Template and Redundant Via Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.1 DSA Feasible Via Pattern Identification . . . . . . . . . . . . . . 16 3.1.2 Conflict Graph Construction . . . . . . . . . . . . . . . . . . . . 20 3.1.3 Maximal Weight Independent Set Calculation . . . . . . . . . . . 23 3.1.3.1 A Greedy Approach . . . . . . . . . . . . . . . . . . . . . 23 3.1.3.2 Optimal Solution of The Maximum Weight Independent Set Problem . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 An Optimal ILP-Based Algorithm for Guiding Template and Redundant Via Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2.1 DSA Feasible Via Pattern Identification . . . . . . . . . . . . . . 26 3.2.2 Basic ILP Formulation . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.3 ILP Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.3.1 Independent Group Computation . . . . . . . . . . . . . 30 3.2.3.2 Reduced Constraints for Detection . . . . . . . . . . . . 31 3.2.3.3 A Special Case . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 Wire Perturbation for DSA-Aware Redundant Via Insertion . . . . . . . 32 3.3.0.4 DSA with Wire Perturbation . . . . . . . . . . . . . . . 33 3.3.0.5 New Conflicting Conditions . . . . . . . . . . . . . . . . 35 3.3.0.6 Cost of Wire Perturbation . . . . . . . . . . . . . . . . . 37 Chapter 4. Experimental Results 38 Chapter 5. Conclusions 48 Bibliography 49 Publication List 53 | |
dc.language.iso | en | |
dc.title | 定向自組裝微影考量導通孔嵌入之綜合優化演算法 | zh_TW |
dc.title | Comprehensive Optimization Algorithms for Directed Self-Assembly (DSA)-Aware Redundant Via Insertion | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 方劭云(Shao-Yun Fang),陳少傑(Sao-Jie Chen),盧奕璋(Yi-Chang Lu) | |
dc.subject.keyword | 實體設計,定向自組裝微影,可製造性設計,冗餘導通孔, | zh_TW |
dc.subject.keyword | Physical Design,Directed Self-Assembly Lithography,Design for Man- ufacturability,Redundant Via, | en |
dc.relation.page | 53 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2015-12-23 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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