使用改良式多閘極電晶體線性化技術之K頻段功率放大器之研究

Abstract

本論文提出一個功率放大器的設計，一使用改良式多閘極電晶體線性化技術之功率放大器。改良式多閘極電晶體線性化功率放大器操作於K頻段，是將傳統多閘極電晶體線性化技術的缺點做進一步改善。傳統多閘極電晶體線性化技術大多是應用於改善小訊號放大器的線性度。功率放大器為了得到較大的功率，必須選擇尺寸較大的電晶體，因此若將多閘極電晶體線性化技術應用於功率放大器設計則需要並聯尺寸較大的電晶體以達到線性化的效果，然而尺寸太大會導致多閘極電晶體的輸入阻抗太小影響整體放大器的電壓增益。本論文提出的改善方式為在輸入端使用共汲極放大器來增加輸入阻抗，可以使增益不會下降太多的情況下，改善大訊號的線性度。為了驗證所提出的線性化技術，我們使用180奈米互補式金氧半導體製程設計一K頻段之線性化功率放大器。量測的OP1dB與其對應之PAE分別14.9 dBm與11.7%，在IMD3 小於 -30 dBc的最大輸出功率為11.9 dBm。靜態直流消耗135毫瓦的功率。與其他發表過的K頻段功率放大器做比較，本電路使用線性化的方法可以使OP1dB與最大輸出功率在IMD3小於 -30 dBc的差值較小，這意味著操作輸出功率離OP1dB很近。

This thesis presents a K-band linearized power amplifier using modified multi-gated transistor technique. The linearized PA using modified multi-gated transistor (MGTR) technique is operated in K-band. Conventional MGTR technique is usually applied to the small-signal amplifier to improve the linearity, and mechanism of linearization is to reduce the third order transconductance (gm3). However, for power amplifier design, a larger transistor size is preferred to have a higher output power, which results in a low input impedance and voltage gain degradation. In order to solve this problem, a common-drain amplifier is added and cascaded with the auxiliary path in a conventional MGTR amplifier to increase the input impedance and improve the voltage gain. To verify the proposed concept, a K-band PA using the proposed modified MGTR technique is developed in 180-nm CMOS process. According to the measurement results, the OP1dB is 14.9 dBm, and the corresponding PAE is 11.7%. The maximum output power for the IMD3 which is less than -30 dBc is 11.9 dBm. The quiescent dc power consumption is 135 mW. Compared with the reported literatures, the proposed PA demonstrates less difference between OP1dB and maximum Pout under below -30 dBc. It means operation output power close to the OP1dB.