具脈波寬度調變抖動之電源轉換器效率模型

Abstract

本論文之研究目的為探討脈波寬度調變責任週期的抖動(Pulse Width Modulation Duty Cycle Jitter，簡稱PWM抖動)對電源轉換造成的影響並建立其效率模型，進而協助設計者避開因為PWM抖動所造成的效率下降。 在本論文中，首先針對PWM抖動的產生與電源轉換器效率進行說明，再簡介同步降壓型直流轉換器(Synchronous Buck DC Converter)架構、動作原理及非理想的等效電路。接著提出用狀態空間平均法(State-Space Averaging Method)，推導PWM抖動對同步降壓型直流轉換器效率造成之影響。根據負載特性的不同，可分為定電阻負載及定電流負載的效率模型推導。並且比較在不同的PWM抖動頻率或抖動比以及電路選件差異之下的效率下降程度。為了使量測更加準確，本論文使用LabVIEW程式控制，建置自動量測系統來消除溫度飄移引發的量測不準確問題。最後，用電路模擬軟體及硬體電路實作驗證本論文提出的效率模型之準確性。

The objective of this thesis is to investigate the impact of the PWM Duty Cycle jitter (PWM Jitter) on the power converter as well as to establish its efficiency model. By adopting a strategy based on the proposed efficiency model, designers can avoid the efficiency drop caused by PWM jitter. In this thesis, the origin of PWM jitter and the efficiency of power converter are presented first. The synchronous buck DC converters are selected for illustration. Next, a methodology by using the state-space averaging method to find out the impact of the PWM jitter on the power conversion efficiency is proposed. Two efficiency models are developed, one for the constant resistance load and the other for the constant current load. Then, the efficiency drops caused by different PWM jitter’s frequency or amplitude are compared. In order to eliminate the measurement inaccuracy caused by the thermal drift, a LabVIEW-based programmable automatic measuring system is established. Finally, the computer simulations and the hardware experiments confirm the accuracy of the proposed efficiency models.