消除數位式多相位延遲鎖定迴路突波的方法

Abstract

本論文提出一種解決多相位延遲鎖定迴路其參考頻率突波的方法。文中探討傳統型延遲鎖定迴路參考突波的成因，並且透過偵測造成突波主因的靜態相位差，達成一個負迴授補償相位差的技巧。此外，有別於傳統型延遲鎖定迴路補捉相位的流程，一個鎖相迴路被共用於多相位延遲鎖定迴路，得以根據即時的頻率變動而自動切換，不需要額外的重置訊號。此多相位延遲鎖定迴路使用Verilog 語言並且透過ISIM模擬實現，輸出頻率為1.6 G赫茲，參考頻率為40 M赫茲，突波被壓抑制至-100 dB/Hz的相位雜訊小於未使用突波消除技術的-65 dB/Hz，均方根的抖動量為1.28 ps。

A digital multiplying delay-locked loops (DMDLL) with a reference spur cancellation technique is presented. At the first, the problem of serious reference spur caused by conventional multiplying delay-locked loops (MDLL) is discussed. By detecting the static phase offset between the reference-signal path and inject-signal path, a negative feedback loop is used to compensate the phase error. Beside, unlike conventional MDLL capture the phase of the process, a digital phase-locked loop (DPLL) is commonly used for the proposed DMDLL, can be switched automatically according to instant frequency variation, no additional reset signal. The proposed DMDLL is implemented in the Verilog language and simulated with ISim simulator. The reference frequency and the output frequency have been set to 40 MHz and 1.6 GHz, respectively. The spur can be pulled down to -100 dB/Hz less than -65 dB/Hz caused by MDLL without the cancellation technique. The root-mean-square jitter is 1.28 ps.