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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/49843完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
| dc.contributor.author | Yu-Hong Yang | en |
| dc.contributor.author | 楊育泓 | zh_TW |
| dc.date.accessioned | 2021-06-15T11:52:01Z | - |
| dc.date.available | 2021-08-24 | |
| dc.date.copyright | 2016-08-24 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-08-11 | |
| dc.identifier.citation | [1] R. B. Staszewski, et al., 'All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13μm CMOS,' Proc. ISSCC Dig. Tech. Papers, pp. 272-273, Feb. 2004.
[2] M. Lee, M. Heidari, and A. A. Abidi, “A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution,” IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2808–2816, Oct. 2009. [3] T. Tokairin, M. Okada, M. Kitsunezuka, T. Maeda, and M. Fukaishi, “A 2.1-to-2.8-GHz low-phase-noise all-digital frequency synthesizer with a time-windowed time-to-digital converter,” IEEE J. Solid-State Circuits, vol. 45, pp. 2582-2590, Dec. 2010. [4] P. Dudek, et al., “A high-resolution time-to-digital converter utilizing a Vernier delay line,” IEEE J. Solid-State Circuits, vol. 35, no.2, pp. 240-247, Feb. 2000. [5] B. Razavi, “Design of integrated circuits for optical communications,” 1st Ed., Mc-Graw Hill, 2003. [6] T.-C. Lee, and K.-J. Hsiao, “The design and analysis of a DLL-based frequency synthesizer for UWB application,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp.1245-1252, Jun. 2006. [7] R. Farjad-Rad, W. Dally, H.-T. Mg, R. Senthinathan, M.-J. Edward Lee, R. Rathi and J. Poulton, “A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp.1804-1812, Dec. 2002. [8] Homayoun and B. Razavi, “Relationship between delay line phase noise and ring oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 49, no. 2, pp.384-391, Feb. 2014. [9] M. H. Perrott, M. D. Trott, and C. G. Sodini, “A modeling approach for Σ-∆ fractional-N frequency synthesizers allowing straightforward noise analysis,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp.1028-1038, Aug. 2002 [10] A. Homayoun and B. Razavi, “Analysis of phase noise in phase/frequency detectors,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 3, pp. 529-539, Mar. 2013. [11] S. Gierkink, “Low-spur, low-phase-noise clock multiplier based on a combination of PLL and recirculating DLL with dual-pulse ring oscillator and self-correcting charge pump,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2967-2976, Dec. 2008. [12] Amr Elshazly, Rajesh Inti, Brian Young and Pavan Kumar Hanumolu, “Clock multiplication techniques using digital multiplying delay –locked loops,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1416-1428, June. 2013. [13] Salvatore Levantino, Giovanni Marucci, Giovanni Marzin, Andrea Fenaroli, Carlo Samori and Andrea L. Lacaita, “A 1.7 GHz fractional-N frequency synthesizer based on a multiplying delay-locked loop” IEEE J. Solid-State Circuits, vol. 50, no. 11, Nov. 2015. [14] B. M. Helal, M. Z. Straayer, G.-Y. Wei, and M. H. Perrott, “A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 855-863, Apr. 2008. [15] Somnath Kundu, Bongjin Kim, Chris H. Kim, “A 0.2-to-1.45 GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection,” Proc. ISSCC Dig. Tech. Papers, Feb. 2016. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/49843 | - |
| dc.description.abstract | 本論文提出一種解決多相位延遲鎖定迴路其參考頻率突波的方法。文中探討傳統型延遲鎖定迴路參考突波的成因，並且透過偵測造成突波主因的靜態相位差，達成一個負迴授補償相位差的技巧。此外，有別於傳統型延遲鎖定迴路補捉相位的流程，一個鎖相迴路被共用於多相位延遲鎖定迴路，得以根據即時的頻率變動而自動切換，不需要額外的重置訊號。此多相位延遲鎖定迴路使用Verilog 語言並且透過ISIM模擬實現，輸出頻率為1.6 G赫茲，參考頻率為40 M赫茲，突波被壓抑制至-100 dB/Hz的相位雜訊小於未使用突波消除技術的-65 dB/Hz，均方根的抖動量為1.28 ps。 | zh_TW |
| dc.description.abstract | A digital multiplying delay-locked loops (DMDLL) with a reference spur cancellation technique is presented. At the first, the problem of serious reference spur caused by conventional multiplying delay-locked loops (MDLL) is discussed. By detecting the static phase offset between the reference-signal path and inject-signal path, a negative feedback loop is used to compensate the phase error. Beside, unlike conventional MDLL capture the phase of the process, a digital phase-locked loop (DPLL) is commonly used for the proposed DMDLL, can be switched automatically according to instant frequency variation, no additional reset signal. The proposed DMDLL is implemented in the Verilog language and simulated with ISim simulator. The reference frequency and the output frequency have been set to 40 MHz and 1.6 GHz, respectively. The spur can be pulled down to -100 dB/Hz less than -65 dB/Hz caused by MDLL without the cancellation technique. The root-mean-square jitter is 1.28 ps. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T11:52:01Z (GMT). No. of bitstreams: 1 ntu-105-R03943015-1.pdf: 2489419 bytes, checksum: dc1ac8be882321dab3465035c2be0164 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 口試委員審定書
誌謝 i 摘要 iii Abstract v Contents vii List of Figures. ix List of Tables xiii Chapter 1 Introduction 1 1.1 Motivation and Research Goals 1 1.2 Thesis Overview 2 Chapter 2 Basic Concepts of Frequency Synthesizers 3 2.1 Basics of Frequency Synthesizers 3 2.2 Basics of Analog PLL-based Frequency Synthesizers 3 2.3 Background of Digital Phase-Locked Loops 5 2.4 Basic of Delay-Locked Loops (DLL) 10 2.5 Basic of DLL-Based Frequency Multiplier 12 2.6 Multiplying DLL 14 2.7 Summary 16 Chapter 3 Relationship between Delay Line Phase Noise and Ring Oscillator Phase Noise 17 3.1 Introduction 17 3.2 Phase Noise of Delay Lines 18 3.3 Phase Noise of Ring Oscillators 20 3.4 Comparison of Delay Lines and Ring Oscillators 24 3.5 Compact Phase Noise Equations 26 Chapter 4 Proposed Digital Multiplying Delay-Locked Loops 29 4.1 Introduction 29 4.2 Proposed Structure 35 4.3 Simulation Results 42 Chapter 5 Circuit Implementation 46 5.1 Circuit Implementation 46 5.2 Chip Configuration 50 5.3 Summary 51 Bibliography 53 Biography 58 | |
| dc.language.iso | en | |
| dc.subject | 頻率合成器 | zh_TW |
| dc.subject | 數位式鎖相迴路 | zh_TW |
| dc.subject | 數位式延遲鎖定迴路 | zh_TW |
| dc.subject | 突波 | zh_TW |
| dc.subject | digital phase-locked loop | en |
| dc.subject | digital multiplying delay-locked loops | en |
| dc.subject | Frequency synthesize | en |
| dc.subject | reference spur | en |
| dc.title | 消除數位式多相位延遲鎖定迴路突波的方法 | zh_TW |
| dc.title | A Spur Cancellation Technique for Digital Multiplying Delay-Locked Loops | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 郭泰豪,劉深淵,黃柏鈞 | |
| dc.subject.keyword | 頻率合成器,數位式鎖相迴路,數位式延遲鎖定迴路,突波, | zh_TW |
| dc.subject.keyword | Frequency synthesize,digital phase-locked loop,digital multiplying delay-locked loops,reference spur, | en |
| dc.relation.page | 58 | |
| dc.identifier.doi | 10.6342/NTU201602218 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2016-08-11 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-105-1.pdf 未授權公開取用 | 2.43 MB | Adobe PDF |
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