應用於相位陣列系統中之線性化功率放大器和相移器

Abstract

本論文目標為設計並實現應用於相位陣列系統中的功率放大器和相移器，其中功率放大器是以65奈米互補式金氧半場效電晶體(CMOS)製程實現而相移器是用0.18微米互補式金氧半場效電晶體(CMOS)製作。功率放大器採用線性化技術並操作於V頻段而相移器是操作於K頻段並且具有低插入損耗變化的特性。 近年來由於無線通訊的快速成長且為了提供更高速的傳輸進而驅使了毫米波頻段的使用。為了增加頻譜的使用效率，現代無線通訊系統都會使用較複雜的調變技術例如:64-QAM。這種調變技術通常需要一個非常線性的功率放大器在發射端以避免信號失真造成對旁頻帶的干擾。為了要達到這樣嚴苛的線性度要求，功率放大器通常會使用功率回調技術(power back-off)來達成對線性度的要求，可是輸出功率在毫米波頻段是非常珍貴的，所以使用功率回退技術會造成效率大幅降低，因此這篇論文第一部分是要設計一個低損耗的內建線性器。 論文的第一部份描述一個在V頻段線性化的功率放大器。在三級功率放大器中，功率級(power stage)利用電流合併的方式合併四個30指閘級寬度2微米的電晶體在加上一個預失真的線性器來提高功率放大器的輸出功率。這個電路是用65奈米互補式金氧半場效電晶體(CMOS)製程實現。當線性器關閉時其輸出功率(P1dB)為10 dBm，效率為5.9%，而當線性器打開時其輸出功率(P1dB)為11.8 dBm，效率為8.4%，損耗為3 dB。就我們所知，這是第一個利用互補式金氧半場效電晶體(CMOS)製程在V頻段實現的預失真功率放大器。 相位陣列系統可以提供高指向性，它的高陣列增益也可增加信號雜訊比。相移器和可變增益放大器是相位陣列系統中的二大主要元件。為了要降低控制相位陣列系統的複雜度，必須能夠獨立的調控其相位和振幅。因此，設計一個低插入損耗變化的相移器和一個低插入相位變化的可變增益放大器是必須的。 論文的第二部份說明一個設計在 22 GHz低插入損耗變化的相移器，並且在21 GHz到25 GHz均擁有超過330度連續可調的角度。此電路是用0.18微米互補式金氧半場效電晶體(CMOS)製作。架構上是由一個180度連續可調式反射式相移器串接上一個180度切換式相移器。量測結果顯示在22 GHz有336度連續可調範圍，插入損耗變化為1.3 dB，而最大插入損耗為16 dB。

The goal of this thesis is to design and to implement a phase shifter and a power amplifier for phase-array system applications. The phase shifter is designed at K-band with continuously phase tuning and with low insertion-loss variation using standard 0.18-μm CMOS process. The power amplifier is implemented at V-band using 65-nm CMOS process with a pre-distortion linearizer. Recently, the demand for wireless communication is growing rapidly that motivates the operation frequency toward millimeter-wave frequency to provide wider bandwidth for Gigabit wireless applications. To enhance spectral efficiency, modern communication system tends to use complex modulation techniques like 64-QAM which requires a highly linear power amplifier in the transmitter. Power back-off techniques is often used to achieve the linearity requirements, but in expense of power-added efficiency (PAE). Therefore, a low-loss built-in linearizer is developed in the first part of this thesis. The first part of the thesis presents linearized power amplifier at V-band. Four 30 finger 2-μm devices are combined using current combining method in the output stage of the three-stage PA and then adding the pre-distortion linearizer to improve the linear output power of the power amplifier. The circuit is designed in 65-nm CMOS process with 10 dBm P1dB and with PAE 6.0% when linearizer is off. When linearizer is on, the P1dB is improved from 10 dBm to 11.8 dBm and the PAE is 8.8% with 3 dB gain degradation. Phase array system is a future trend for millimeter-wave frequency as the higher directivity and higher array gain can increase signal-to-noise ratio (SNR). Phase shifter and variable gain amplifier (VGA) are both the critical part of the system. However, to reduce the control complexity, phase and amplitude must be control independently. Therefore, a low insertion-loss variation phase shifter and a low phase variation VGA must be developed respectively. The second part of the thesis demonstrates a low insertion-loss variation phase shifter at 22 GHz with over 330∘continuously phase tuning range from 21-25 GHz in standard 0.18-μm CMOS technology. This phase shifter is composed of a 180∘continuously phase tuning range reflection-type phase shifter (RTPS) and a 180∘discrete switch-type phase shifter (STPS). The measured phase shift range is 336∘at 22 GHz with small loss variation of 1.3 dB at 22 GHz and the maximum insertion loss at 22 GHz is 16 dB.