請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/47458完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
| dc.contributor.author | Meng-Fan Wu | en |
| dc.contributor.author | 吳孟帆 | zh_TW |
| dc.date.accessioned | 2021-06-15T06:00:45Z | - |
| dc.date.available | 2011-08-19 | |
| dc.date.copyright | 2010-08-19 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-16 | |
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Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding. In Proc. IEEE Conf. on Computer Design, pages 474–479, 2002. [41] P. M. Rosinger, B. M. Al-Hashimi, and N. Nicolici. Scan Architecture with Mutually Exclusive Scan Segment Activation for Shift and Capture Power Reduction. IEEE Transactions on Very Large Scale Integration Systems, pages 1142–1153, 2004. [42] J. P. Roth. Diagnosis of Automata Failures: a Calculus and a Method. IBM Journal of Research and Development, 10(4):278–291, 1966. [43] R. Sankaralingam, R. Oruganti, and N. Touba. Static Compaction Techniques to Control Scan Vector Power Dissipation. In Proc. VLSI Test Symposium, pages 35–40, 2000. [44] R. Sankaralingam, B. Pouya, and N. Touba. Reducing Power Dissipation during Test Using Scan Chain Disable. In Proc. VLSI Test Symposium, pages 319–324, 2001. [45] R. Sankaralingam and N. Touba. Controlling Peak Power during Scan Testing. In Proc. VLSI Test Symposium, pages 153–159, 2002. [46] J. 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IEEE Design and Test of Computers, 23(6):294–303, Apr. 2006. [52] J. Wang, D. M. H. Walker, A. Majhi, B. Kruseman, G. Gronthoud, L. E. Villagra, P. van de Wiel, and S. Eichenberger. Power Supply Noise in Delay Testing. In Proc. International Test Conference, pages 17.3.1–17.3.10, 2006. [53] S. Wang and S. K. Gupta. An Automatic Test Pattern Generator for Minimizing Switching Activity During Scan Testing Activity. IEEE Transactions on Computer-Aided Design, 21(8):954–968, Aug. 2002. [54] S.Wang and W.Wei. A Technique to Reduce Peak Power Current and Average Power Dissipation in Scan Designs by Limited Capture. In Proc. Asian S. Pacific Design Automation Conf., pages 810–816, 2007. [55] X. Wen, S. Kajihara, K. Miyase, T. Suzuki, K. K. Saluja, L.-T. Wang, K. S. Abdel-Hafez, and K. Kinoshita. A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. In Proc. VLSI Test Symp., pages 58–65, 2006. [56] X. Wen, K. Miyase, S. Kajihara, H. Furukawa, Y. Yamato, A. Takashima, K. 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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/47458 | - |
| dc.description.abstract | 掃描鏈測試是積體電路測試中廣泛使用的方式，而自動測試向量產生方法已經被研究了數十年。雖然自動測試向量產生方法是傳統的設計自動化問題，現代低電壓、高頻、高複雜度的設計已經大幅改變了此問題。因此，在產生向量檔的過程中，還需要同時去考慮各種不同的問題。例如，測試功率的消耗、測試向量的壓縮、以及全速測試過程中過量的電壓降對良率的影響。假如我們能在測試向量產生過程中考慮這些問題，將能夠提升測試向量檔的品質。
在這份論文當中，我們提出了數個演算法在產生測試向量檔的同時，考慮測試功率、可壓縮性、與電壓降效應。這份論文在一開始提出了一個新技術，來減少基本的測試過程中測試功率以及引發之電壓降。之後，我們提出新的技術將典型的電壓降減少方法成功地應用到測試向量壓縮環境。最後，為了減少因電壓降估算誤差所造成的可靠度下降，我們提出了一個快速的，藉由考慮電源網架構來增加精確度的電壓降估算方法。 | zh_TW |
| dc.description.abstract | Scan testing is a widely used test methodology in the industry and the automatic test pattern generation (ATPG) problem has been studied for several decades.Although ATPG is a classical problem, modern high operating frequency, low-power, and high complexity circuit designs have posed new challenges. Thus, during test pattern generation, in addition to fault coverage and test pattern count, one has to consider test power dissipation, test pattern compression, and excessive IR-drop effects on at-speed scan testing. If we can consider above issues while generating test patterns, the test set quality could be improved.
In this dissertation, we propose several algorithms and techniques to consider test power dissipation, test compressibility, and IR-drop effects in ATPG. This dissertation starts with a new technique, which aims at reducing test power and IR-drop effects during the whole scan test application process. Next, we propose an efficient and effective flow to alleviate launch cycle IR-drop effects by minimizing launch cycle switching activity in the test compression environment. Finally, to improve the IR-drop estimation accuracy, we propose a scalable quantitative measure of IR-drop effects which improve the accuracy by considering the power grid structure. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T06:00:45Z (GMT). No. of bitstreams: 1 ntu-99-F94921096-1.pdf: 6091583 bytes, checksum: 9a8af442a95c9767af8191758c429771 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | Abstract (Chinese) v
Abstract vi List of Tables x List of Figures xi Chapter 1. Introduction 1 1.1 Test Pattern Generation System . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Test Pattern Generation Basics . . . . . . . . . . . . . . . . . . . . . . . 3 1.2.1 Basic Algorithmic Method for Pattern Generation . . . . . . . . . 3 1.2.2 Scan Test Application . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2.3 Low-Power TPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.4 Test Pattern Compression . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.5 IR-Drop Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3 Modern Test Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3.1 IR-Drop Effects in Shift Mode . . . . . . . . . . . . . . . . . . . . 17 1.3.2 IR-Drop Effects in Test Compression Environment . . . . . . . . . 18 1.3.3 Scalable Quantitative Measure of IR-Drop Effects . . . . . . . . . . 19 1.4 Overview of the Dissertation . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4.1 Peak and Average Power During Scan Test Application . . . . . . 19 1.4.2 Launch Cycle IR-Drop in Linear-Decompressor Environment . . . 20 1.4.3 A Scalable Quantitative Measure of IR-Drop Effects . . . . . . . . 20 1.5 Organization of the Dissertation . . . . . . . . . . . . . . . . . . . . . . . 20 Chapter 2. Peak and Average Power During Scan Test Application 22 2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2 The Proposed Low-Power ATPG Methodology . . . . . . . . . . . . . . . 22 2.2.1 LPTest Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.2 Peak WFSA Cost Function . . . . . . . . . . . . . . . . . . . . . . 24 2.2.3 Estimating WFSA of Partially Specified Patterns . . . . . . . . . . 27 2.2.4 WFSA-Aware Test Generation Engine . . . . . . . . . . . . . . . . 29 2.2.5 WFSA Constrained Dynamic Compaction . . . . . . . . . . . . . . 29 2.2.6 Low-Power X-Filling . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.7 Extension to At-Speed Testing . . . . . . . . . . . . . . . . . . . . 32 2.2.8 Extension to Capture Power Reduction . . . . . . . . . . . . . . . 33 2.2.9 Iterative Test Set Refinement . . . . . . . . . . . . . . . . . . . . . 33 2.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3.1 Peak WSA Reduction . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3.2 Details of the Iteration Flow . . . . . . . . . . . . . . . . . . . . . 39 2.3.3 Average WSA Reduction . . . . . . . . . . . . . . . . . . . . . . . 39 Chapter 3. Launch Cycle IR-Drop in Linear-Decompressor Environment 45 3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2 Compressible Power Supply Noise Reduced Test Pattern Generation . . . 46 3.2.1 Implied and Free X Bits . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.2 CSNR-Test Overview . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.3 Compressible Power Supply Noise Reduced (CSNR) ATPG . . . . 50 3.3 Compressible JP-Filling (CJP-Filling) . . . . . . . . . . . . . . . . . . . . 52 3.3.1 A Naive Compressible JP-filling Flow . . . . . . . . . . . . . . . . 52 3.3.2 The Proposed CJP-Filling Flow . . . . . . . . . . . . . . . . . . . 54 3.3.3 CJP-Filling Performance Analysis . . . . . . . . . . . . . . . . . . 57 3.3.4 Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.4.1 EDT-Standard versus CSNR-Test . . . . . . . . . . . . . . . . . . 59 3.4.2 Impact of X-Ratio Threshold . . . . . . . . . . . . . . . . . . . . . 61 3.4.3 Further Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Chapter 4. Scalable Quantitative Measure of IR-Drop Effects 65 4.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.2 The Whole-Chip IR-Drop Estimation Technique . . . . . . . . . . . . . . 66 4.2.1 The Power Grid Model . . . . . . . . . . . . . . . . . . . . . . . . 67 4.2.2 MNA-Based IR-Drop Computation . . . . . . . . . . . . . . . . . . 68 4.2.3 Proposed IR-Drop Estimation Flow . . . . . . . . . . . . . . . . . 68 4.2.4 Weight Vector Computation . . . . . . . . . . . . . . . . . . . . . 69 4.2.5 PBP IR-Drop Profile Computation . . . . . . . . . . . . . . . . . . 69 4.2.6 Whole-Chip IR-Drop Profile Computation . . . . . . . . . . . . . . 70 4.2.7 Applicability to Complex Power Distribution Network . . . . . . . 71 4.3 Launch Cycle IR-Drop Estimation Flow . . . . . . . . . . . . . . . . . . . 71 4.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.4.1 Global Peak IR-Drop Evaluation . . . . . . . . . . . . . . . . . . . 74 4.4.2 Regional IR-Drop Evaluation . . . . . . . . . . . . . . . . . . . . . 76 4.4.3 Snapshots Correlation Summary . . . . . . . . . . . . . . . . . . . 77 4.5 Scalable Implementation Method . . . . . . . . . . . . . . . . . . . . . . 77 4.5.1 Pre-processing phase . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.5.2 Operating phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.5.3 Resulting Whole-Chip IR-Drop Profile for the Industrial Design . . 82 4.6 Summary of WSAWT+ and SIEAP . . . . . . . . . . . . . . . . . . . . . . 85 4.7 An Example of PIM Usages for Pattern Generation Guidance . . . . . . . 85 4.7.1 Correction on the Pre-Defined Range . . . . . . . . . . . . . . . . 85 Chapter 5. Concluding Remarks and Future Work 89 5.1 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Bibliography 91 Vita 98 Publication List 99 | |
| dc.language.iso | en | |
| dc.subject | 測試向量壓縮 | zh_TW |
| dc.subject | 積體電路測試 | zh_TW |
| dc.subject | 低功率測試 | zh_TW |
| dc.subject | 電壓降關切測試 | zh_TW |
| dc.subject | VLSI Testing | en |
| dc.subject | Test Compression | en |
| dc.subject | IR-Drop-Aware Test | en |
| dc.subject | Low-Power Test | en |
| dc.title | 考慮測試功率、可壓縮性、以及電壓降效應之測試向量產生方法 | zh_TW |
| dc.title | Scan Test Pattern Generation Considering Test Power, Compressibility, and IR-Drop Effects | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 李昆忠(Kuen-Jong Lee),王行健(Sying-Jyan Wang),溫曉青(Xiaoqing Wen),李建模(Chien-Mo Li) | |
| dc.subject.keyword | 積體電路測試,低功率測試,電壓降關切測試,測試向量壓縮, | zh_TW |
| dc.subject.keyword | VLSI Testing,Low-Power Test,IR-Drop-Aware Test,Test Compression, | en |
| dc.relation.page | 100 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-08-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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