IEEE 802.16-2004 基頻接收機之數位訊號處理器軟體實現

Abstract

本論文根據802.16-2004 OFDM標準提出一用戶端基頻實體層收發機之架構。在基頻通道模型包含SUI通道模型、加成性白色高斯雜訊、載波頻率飄移以及取樣時脈飄移的前提下，接收機則運用合適的演算法來進行符元邊界偵測、載波頻率飄移和取樣時脈之偵測補償、頻率等化器與內插器等來進行資料回復。進一步在德州儀器(TI)的TMS320C6416 DSP來模擬軟體實現，並藉由一連串的軟體開發流程來降低內接收機所需運行的時脈數以達到及時運算的要求。

In this Thesis, we propose a baseband physical layer transceiver architecture according to the 802.16-2004 OFDM specifications. The baseband channel model is defined according to the SUI channel model, with Additive White Gaussian Noise (AWGN), carrier frequency offset, and sampling clock offset. To recover the data, suitable algorithms are used to detect the symbol boundary, to estimate and compensate carrier frequency offset and sampling clock offset, to interpolate, and to perform the frequency-domain equalization in the receiver. Moreover, the TMS320C6416 DSP of Texas Instruments (TI) is used in software implementation. By a sequence of code development flow, the operation cycles are reduced and the inner receiver is able to meet the real time requirement.