使用資料相依性同步與排程演算法加速系統晶片虛擬平台之模擬

Abstract

在本篇論文中，我們針對系統晶片虛擬平台之模擬，提出了「資料相依性同步與排程」的模擬方案。此模擬方案有別於傳統的單一時脈來進行同步模擬，及不同於傳統以訊號交易為基礎來進行同步模擬；我們利用結合「模擬平台上各模組的時脈解耦」和「直接資料存取」兩種技術，將蹤跡模擬法應用到系統晶片虛擬平台的模擬上。此外，我們導入虛擬同步的概念於此模擬方案中，使虛擬平台能夠模擬系統的中斷訊號發生，進而有助於作業系統在虛擬平台上之移植。我們利用在SystemC的核心外包裝一個前置處理系統，使得原有以SystemC語言建置的虛擬平台系統，可以盡量在不修改原有式碼的情況下，依照我們所提出的模擬方案來進行虛擬平台之模擬。實驗結果顯示，「資料相依性同步與排程」的模擬方案可以在維持相同模擬時脈數的精準度下，將虛擬平台的模擬速度提升到每秒三百萬到五百萬指令數；這樣的模擬速度大約是44倍快於傳統SystemC核心的模擬速度。

In this thesis, we proposed a novel simulation scheme, called data-dependency-aware synchronization and scheduling, for SoC virtual platform simulation. In contrast to the conventional clock-based or transaction-based synchronization, our simulation scheme works with the clock decoupling and direct-data-access techniques to implement the trace-driven virtual synchronization methodology. In addition, we further extend the virtual synchronization concept to handle the interrupt signals in the system. This enables the porting of operating system in the virtual platform. We realize our simulation scheme of the data-dependency-aware synchronization and scheduling by implementing a simulation wrapper on top of the SystemC kernel. The experimental results show that virtual platform can achieve 3 to 5 million-instructions-per-second simulation speed, while still maintaining the same cycle-count accuracy, which is around 44 times speed-up over the conventional cycle accurate approach of SystemC kernel.