一個適用於管線式類比數位轉換器的放大器閉迴路增益誤差自我校正技術

Abstract

近年來，管線式類比數位轉換器被普遍地應用在中解析度且高速的無線通訊系統中。隨著製程的進步，元件尺寸縮小使得寄生電容大幅降低，電路的速度也隨之提升。但是對於類比電路而言，工作電壓的降低加上本質增益的減少，導致高增益放大器的設計難度日漸提升，也影響到了高速管線式類比數位轉換器的解析度與正確性。 本論文闡述一個適用於管線式類比數位轉換器的放大器閉迴路增益誤差自我校正技術，並且在一個十位元管線式類比數位轉換器實現此校正技術。此管線式類比數位轉換器以台積電 90nm CMOS製程製作，並且採用了一個操作在1.2伏特的低增益高頻寬放大器來提升整體工作速度，而低增益放大器所帶來的閉迴路增益誤差問題則可有效地被校正至所需的解析度。 依據量測的結果，本晶片操作在40MS/s的取樣頻率下，DNL從校正前的+1.73/-1 LSB 改善至 +0.77/-0.55 LSB，INL則從+13.97/-14.39 LSB 改善至+1.45/-1.03 LSB。對於20MS/s的信號輸入頻率，在80MS/s的取樣頻率下，SNDR為54.95dB，SFDR為63.96dB。當時脈升至320MS/s時，SNDR與SFDR則為53.43dB與61.80dB。在320MS/s的轉換速率下，功率消耗為47.2mW。晶片總面積占0.86mm2。 在第一章中，將介紹研究動機與論文架構。第二章討論介紹管線式類比數位轉換器之架構與電路非理想效應帶來的影響。第三章說明所提出來的自我校正方法，用來改善閉迴路增益誤差。電路細節與模擬結果包含在第四章。第五章呈現量測的設定與量測結果，最後於第六章中對此校正方法與電路做總結。

This thesis presents a closed-loop gain-error self-calibration technique for pipelined ADCs, and the proposed calibration method is used in a 1.2V 10-bit pipelined ADC. The proposed pipelined ADC is design in TSMC 90nm CMOS process. A two-stage operational amplifier (opamp) with low DC gain is utilized to the multiplying DACs (MDACs). The proposed gain-error self-calibration technique allows low-gain opamps used in high-precision MDACs for pipelined ADCs. The proposed technique reduces gain error by using a calibration capacitor array. It adjusts the feedback factor; therefore, the closed-loop gain is calibrated. According to the measurement results, DNL of the proposed ADC is improved from +1.73/-1 LSB to +0.77/-0.55 LSB, and INL is improved from +13.97/-14.39 LSB to +1.45/-1.03 LSB at 40MS/s. At the sampling rate of 80MS/s, for 20MHz input frequency, the SNDR and SFDR are 54.95 dB and 63.96 dB. At 320MS/s, the SNDR and SFDR are reduced to 53.43 dB and 61.80 dB for 40MHz input. The power consumption is 47.2mW at the conversion rate of 320MS/s. The chip with pads occupies 0.86mm2.