一個適用於管線式類比數位轉換器的放大器閉迴路增益誤差自我校正技術

Wei-Ting Shen; 沈威廷

請用此 Handle URI 來引用此文件： http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45044

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.advisor	陳信樹
dc.contributor.author	Wei-Ting Shen	en
dc.contributor.author	沈威廷	zh_TW
dc.date.accessioned	2021-06-15T04:02:24Z	-
dc.date.available	2013-03-11
dc.date.copyright	2010-03-11
dc.date.issued	2010
dc.date.submitted	2010-02-19
dc.identifier.citation	[1] Mikael Gustavsson, J. Jacob Wikner and N. Nick Tan, CMOS Data Converters for Communications. Kluwer Academic Publishers, 2000. [2] B.Razavi, Principles of Data Conversion System Design. Wiley-IEEE Press, 1995. [3] Rudy van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 2003. [3] Mikael Gustavsson, J. Jacob Wikner and N. Nick Tan, CMOS Data Converters for Communications. Kluwer Academic Publishers, 2000. [4] S. H. Lewis, H. S. Fetterman, G. F. Gross Jr., R. Ramachandran, and T. R. Viswanathan, “A 10-b 20-Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992. [5] T. Cho and P. R. Gray, “A 10 b 20 Msamples/s, 35 mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 30, pp. 166–172, Mar. 1995. [6] F. Maloberti, F. Francesconi, P. Malcovati, and O. J. A. P. Nys, “Design considerations on low-voltage low-power data converters,” IEEE Trans. Circuits Syst. I, vol. 42, pp. 853–863, Nov. 1995. [7] Y. M. Lin, B. Kim, and P. R. Gray, “A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3u CMOS,” IEEE J. Solid-State Circuits, vol. 26, pp. 628-636, Apr. 1991. [8] B. Razavi and B. A. Wooley, “Design Techniques for High-Speed, High-Resolution Comparators,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec. 1992. [9] B. Hernes, A. Briskemyr, T. N. Andersen, F. Telstø, T. E. Bonnerud, and Ø. Moldsvor, “A 1.2 V 220MS/s 10b pipeline ADC implemented in 0.13μm digital CMOS,” ISSCC Dig. Tech. Papers, pp. 256-257, Feb. 2004. [10] Behzad Razavi, Design of Analog CMOS Integrated Circuits. New-York: McGraw-Hill, 2001. [11] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997. [12] Byung-Moo Min, P. Kim, F. W. Bowman, III, D. M. Boisvert, and A. J. Aude, “A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 38, pp. 2031-2039, Dec. 2003. [13] NATIONAL INSTRUMENTS, “DAQ M Series User Manual,” Nov. 2006. [14] J. Doernberg, H. Lee, and D. A. Hodges, “Full-speed testing of A/D converters,” IEEE J. Solid-State Circuits, vol. 19, No. 6, pp. 820-827, Dec. 1984. [15] Kang-Wei Hsueh, Yu-Kai Chou, Yu-Hsuan Tu, Yi-Fu Chen, Ya-Lun Yang, Hung-Sung Li, “A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS, ” in ISSCC Dig. Tech. Papers, pp. 546–634, Feb. 2008. [16] Seung-Chul Lee; Young-Deuk Jeon; Kwi-Dong Kim; Jong-Kee Kwon; Jongdae Kim; Jeong-Woong Moon; Wooyol Lee, “A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications, ” in ISSCC Dig. Tech. Papers, pp. 458–615, Feb. 2007.
dc.identifier.uri	http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45044	-
dc.description.abstract	近年來，管線式類比數位轉換器被普遍地應用在中解析度且高速的無線通訊系統中。隨著製程的進步，元件尺寸縮小使得寄生電容大幅降低，電路的速度也隨之提升。但是對於類比電路而言，工作電壓的降低加上本質增益的減少，導致高增益放大器的設計難度日漸提升，也影響到了高速管線式類比數位轉換器的解析度與正確性。本論文闡述一個適用於管線式類比數位轉換器的放大器閉迴路增益誤差自我校正技術，並且在一個十位元管線式類比數位轉換器實現此校正技術。此管線式類比數位轉換器以台積電 90nm CMOS製程製作，並且採用了一個操作在1.2伏特的低增益高頻寬放大器來提升整體工作速度，而低增益放大器所帶來的閉迴路增益誤差問題則可有效地被校正至所需的解析度。依據量測的結果，本晶片操作在40MS/s的取樣頻率下，DNL從校正前的+1.73/-1 LSB 改善至 +0.77/-0.55 LSB，INL則從+13.97/-14.39 LSB 改善至+1.45/-1.03 LSB。對於20MS/s的信號輸入頻率，在80MS/s的取樣頻率下，SNDR為54.95dB，SFDR為63.96dB。當時脈升至320MS/s時，SNDR與SFDR則為53.43dB與61.80dB。在320MS/s的轉換速率下，功率消耗為47.2mW。晶片總面積占0.86mm2。在第一章中，將介紹研究動機與論文架構。第二章討論介紹管線式類比數位轉換器之架構與電路非理想效應帶來的影響。第三章說明所提出來的自我校正方法，用來改善閉迴路增益誤差。電路細節與模擬結果包含在第四章。第五章呈現量測的設定與量測結果，最後於第六章中對此校正方法與電路做總結。	zh_TW
dc.description.abstract	This thesis presents a closed-loop gain-error self-calibration technique for pipelined ADCs, and the proposed calibration method is used in a 1.2V 10-bit pipelined ADC. The proposed pipelined ADC is design in TSMC 90nm CMOS process. A two-stage operational amplifier (opamp) with low DC gain is utilized to the multiplying DACs (MDACs). The proposed gain-error self-calibration technique allows low-gain opamps used in high-precision MDACs for pipelined ADCs. The proposed technique reduces gain error by using a calibration capacitor array. It adjusts the feedback factor; therefore, the closed-loop gain is calibrated. According to the measurement results, DNL of the proposed ADC is improved from +1.73/-1 LSB to +0.77/-0.55 LSB, and INL is improved from +13.97/-14.39 LSB to +1.45/-1.03 LSB at 40MS/s. At the sampling rate of 80MS/s, for 20MHz input frequency, the SNDR and SFDR are 54.95 dB and 63.96 dB. At 320MS/s, the SNDR and SFDR are reduced to 53.43 dB and 61.80 dB for 40MHz input. The power consumption is 47.2mW at the conversion rate of 320MS/s. The chip with pads occupies 0.86mm2.	en
dc.description.provenance	Made available in DSpace on 2021-06-15T04:02:24Z (GMT). No. of bitstreams: 1 ntu-99-R96943143-1.pdf: 1838134 bytes, checksum: 11e3c5bf2a6090d8c8d6677009d708dc (MD5) Previous issue date: 2010	en
dc.description.tableofcontents	ACKNOWLEDGMENT I 摘要 II ABSTRACT III TABLE OF CONTENTS IV LIST OF FIGURES VI LIST OF TABLES VIII CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 2 CHAPTER 2 FUNDAMENTALS OF PIPELINED A/D CONVERTER 3 2.1 PERFORMANCE METRICS 3 2.1.1 DIFFERENTIAL NONLINEARITY (DNL) 3 2.1.2 INTEGRAL NONLINEARITY (INL) 4 2.1.3 OFFSET ERROR 5 2.1.4 GAIN ERROR 5 2.1.5 SIGNAL-TO-NOISE RATIO (SNR) 5 2.1.6 TOTAL HARMONIC DISTORTION (THD) 5 2.1.7 SPURIOUS-FREE DYNAMIC RANGE (SFDR) 6 2.1.8 SIGNAL-TO-NOISE AND DISTORTION RATIO (SNDR) 6 2.1.9 EFFECTIVE NUMBER OF BITS (ENOB) 6 2.2 GENERAL PIPELINED A/D CONVERTER 7 2.2.1 A BASIC 1.5-BIT PER STAGE ARCHITECTURE 9 2.2.2 ERROR SOURCE IN PIPELINED A/D CONVERTER 12 CHAPTER 3 PROPOSED GAIN-ERROR SELF-CALIBRATION TECHNIQUE FOR PIPELINED ADCS 16 3.1 INTRODUCTION 16 3.2 PROPOSED 2.5-BIT MDAC ARCHITECTURE 17 3.3 PIPELINED ADC MODEL 19 3.4 PROPOSED GAIN-ERROR SELF-CALIBRATION TECHNIQUE 20 3.5 OPAMP INPUT-REFERRED OFFSET CONSIDERATION 23 CHAPTER 4 CIRCUIT IMPLEMENTATION AND SIMULATION RESULTS 26 4.1 INTRODUCTION 26 4.2 PROPOSED 10-BIT PIPELINED ADC WITH SELF-CALIBRATION TECHNIQUE 26 4.2.1 PROPOSED PIPELINED ADC ARCHITECTURE 26 4.2.2 PROPOSED 2.5-BIT FULLY-DIFFERENTIAL MDAC ARCHITECTURE 28 4.2.3 REFERENCE VOLTAGES FOR CALIBRATION 30 4.2.4 CALIBRATION CAPACITOR ARRAY 31 4.2.5 OPERATIONAL AMPLIFIER 33 4.2.6 LATCH-TYPE COMPARATOR [12] 34 4.2.7 SUCCESSIVE-APPROXIMATION REGISTERS 35 4.2.8 CALIBRATION TIMING CONSIDERATION 36 4.3 SIMULATION RESULTS 37 4.3.1 MATLAB BEHAVIOR MODEL SIMULATION 37 4.3.2 HSPICE SIMULATION 39 4.3.2.1 Opmap AC analysis 39 4.3.2.2 MDAC output transient analysis 40 4.3.2.3 MDAC calibration analysis with offset 41 4.3.2.4 Full-chip simulation 43 4.3.3 Summary 44 CHAPTER 5 TEST SETUP AND MEASUREMENT RESULTS 45 5.1 INTRODUCTION 45 5.2 TEST SETUP 45 5.3 CONTROL INTERFACE DESIGN 51 5.4 PCB DESIGN 51 5.5 FLOOR PLAN AND LAYOUT CONSIDERATIONS 54 5.6 EXPERIMENT RESULTS 57 5.6.1 TIME DOMAIN DIGITAL CODE OBSERVATION 57 5.6.2 STATIC PERFORMANCE 58 5.6.3 DYNAMIC PERFORMANCE 60 5.7 SUMMARY 64 CHAPTER 6 CONCLUSIONS AND FUTURE WORKS 67 6.1 CONCLUSIONS 64 6.2 FUTURE WORKS 64 BIBLIOGRAPHY 69
dc.language.iso	en
dc.title	一個適用於管線式類比數位轉換器的放大器閉迴路增益誤差自我校正技術	zh_TW
dc.title	A Closed-Loop Gain-Error Self-Calibration Technique for Pipelined ADCs	en
dc.type	Thesis
dc.date.schoolyear	98-1
dc.description.degree	碩士
dc.contributor.oralexamcommittee	林宗賢,蔡宗亨,顧孟愷
dc.subject.keyword	類比數位轉換器,管線式類比數位轉換器,自我校正,增益誤差,	zh_TW
dc.subject.keyword	A/D Converters,Pipelined ADC,Self Calibration,Gain Error,	en
dc.relation.page	71
dc.rights.note	有償授權
dc.date.accepted	2010-02-22
dc.contributor.author-college	電機資訊學院	zh_TW
dc.contributor.author-dept	電子工程學研究所	zh_TW
顯示於系所單位：	電子工程學研究所

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