一個操作在1.2伏特電壓的高速單通道之管線式類比數位轉換器

Abstract

近年來許多研究專注於管線式類比數位轉換器的數位校正，在此篇論文裡介紹一個增益誤差校正技術，可利用低增益放大器來製作高解析的類比數位轉換器，此技術利用校正電容陣列來調整回授因子，因此回授增益也跟著做校正來減少增益誤差。在此電路設計中，我們使用39.1dB放大增益的放大器來實現十位元的管線式類比數位轉換器，此前景式校正技術只需要192個轉換時脈即可完成校正。 根據量測結果，本晶片在40MHz的轉換頻率下的DNL和INL分別為+0.77/-0.55LSB和+1.45/-1.03LSB，在輸入頻率為20MHz且工作在80MHz的轉換頻率下時，量測到的SNDR和SFDR分別為54.97dB和63.96dB，把輸入頻率提高到40MHz且工作在320MHz的轉換頻率時，其SNDR和SFDR分別為53.43dB和61.8dB，操作在1.2伏特電壓時功率消耗為47.2mW，全部的晶片面積大小為0.93mm2，然而主動電路所占的面積只有0.21mm2。

The pipelined ADCs with the digital calibrations have been researched in recently years. In this thesis, a gain-error self-calibration technique is presented to allow low-gain operation amplifiers (opamps) to use in high-precision pipelined ADCs. The proposed technique reduces gain error by using a calibration capacitor array. It adjusts the feedback factor; therefore, the closed-loop gain is calibrated. In the circuit design, 39.1dB open-loop gain opamps can be used for a 10-bit pipelined ADC. Only 192 clock cycles are required for the proposed foreground self-calibration technique. According to the measurement results, the prototype ADC exhibits a DNL of +0.77/-0.55LSB and an INL of +1.45/-1.03LSB at the sampling rate of 40MS/s. With 20MHz input frequency, the SNDR and SFDR achieve 54.97dB and 63.96dB at 80MS/s. The SNDR and SFDR are 53.43dB and 61.8dB at 320MS/s with 40MHz input. The power consumption is 47.2mW at 1.2V supply. The active area is 0.21mm2 and whole chip with pads occupies 0.93mm2.