液晶顯示器源極驅動積體電路之電流內插數位類比轉換器

Abstract

近年來由於超薄外形、重量輕與低成本等因素，使得薄膜電晶體液晶顯示器廣泛的使用。隨著液晶顯示器的快速發展，其驅動器需具備低功率、高解析度與高速的特性。為了實現高品質的畫面，液晶顯示器中的源極驅動器是特別重要的。以八位元的源極驅動器為例，數位類比轉換器就佔了超過50%的面積。 為了減少數位類比轉換器的面積，本論文設計並且實現電流內插數位類比轉換器。所提出的數位類比轉換器包含循環式數位類比轉換器與電流內插電路。信號處理過程是先將數位輸入資料轉換成線性類比電壓，接著處理伽瑪校正的部分，也就是將線性類比電壓轉換成非線性電壓。循環式數位類比轉換器負責線性的數位類比轉換，而電流內插電路則藉由片段線性近似法將線性曲線轉換成非線性。使用循環式數位類比轉換器的好處是只需儲存單一位元資料以執行轉換，因此對於十位元的源極驅動器而言，儲存器與準位昇壓器的數目可節省90%。電流內插方式是首度被提出來使用於源極驅動器中以處理非線性的要求。此外，藉由多工結構可進一步有效地減少所設計的數位類比轉換器之面積，並維持循環式數位類比轉換器、電流內差電路與輸出緩衝器的操作速度。我們採用台積電0.35微米的5伏CMOS製程成功地製造出所構想的十位元數位類比轉換器，4個通道的核心面積為0.215

In recent years, applications of thin-film transistor (TFT) liquid crystal displays (LCDs) have rapidly increased due to their thin shape, light weight, and low cost. With the rapid evolution of LCD, a substantial demand develops LCD drivers with low power consumption, as well as high resolution and high speed. The source driver is especially critical for achieving high-quality display. The digital-to-analog converters (DACs) occupy more than 50% of the area of an 8-bit source driver area. In order to reduce the DAC area, this thesis presents the design and implementation of a current interpolation DAC. The proposed DAC includes a cyclic DAC and current interpolation circuit. The signal processing aims to convert the digital input data into a linear analog voltage, and then change this voltage into a nonlinear voltage for gamma correction. The cyclic DAC performs linear D/A conversion, and the current interpolation circuit is used to transform the linear curve to nonlinear form by piecewise linear approximation. The benefit of using cyclic DACs is that only one bit of data needs to be stored for single-bit conversion. In a 10-bit source driver, for example, a 90% reduction in storages and level shifters is reflected. The current interpolation scheme is proposed for the LCD source driver to deal with the nonlinear requirement. In addition, the N-way-interleaved architecture is used to reduce the proposed DAC area further, and maintain optimum operation speed of cyclic DAC, circuit interpolation circuit, and output buffer. The proposed 10-bit DAC was successfully fabricated in TSMC 0.35-μm 5-V CMOS technology, and the core area is 0.215