H.264全二位元移動偵測之有效率可測試性設計技術

Abstract

H.264是目前擁有最高編碼效率的最新視訊壓縮規格，完整搜尋整數移動偵測(FSIME)與全二位元整數移動偵測(ABIME)這兩種演算法，分別常被使用在獲取最好品質與減少硬體面積的需求上。然而由於近年來視訊解析度快速成長，晶片面積仍然大量增加，因此視訊晶片的可測試性越來越重要，幸運的是在H.264-IME的硬體設計中有大量重複的模組，因此著名的重複邏輯陣列測試法(Iterative-Logic-Array, ILA)可以被用來測試所有重複的模組，而且僅需要固定常數的測試樣本。在重複邏輯陣列測試法中最重要的條件在於每個重複模組的輸入輸出特性必須滿足雙向可逆(bijective, or reversible)，然而大部份的硬體設計通常都不會滿足此一條件。在這篇論文中，將會提出基於重複邏輯陣列測試法的可測試性設計(design-for-testability)，能有效地測試H.264-FSIME與H.264-ABIME兩種演算法的設計模塊。這些重複模組將會被修改成滿足雙向可逆的條件，然後將這些模組串接成重複邏輯陣列的架構，如此只要完整測試第一個模組，便能完整測試陣列中的每個模組。在論文中也提出了一個簡單的內建測試電路。最後，著名的掃描鍊泛型測試法(scan-chain)與本論文提出的測試法都使用聯電(UMC) 0.18um製程合成(synthesize)並實作出來，本測試法的總測試時間大約只有掃描鍊測試法加上自動測試樣本產生器(Automatic Test Pattern Generation, ATPG)的13.53%，而且僅需要少量的額外硬體面積與延遲時間。

H.264 is the latest video compression standard with the highest coding efficiency, and the Full-Search and All-Binary Integer Motion Estimation (FSIME and ABIME) algorithms are usually adopted for getting best performance and reducing hardware area, respectively. However, the chip-area still increases significantly since the video resolution grows rapidly. Thus the testability is becoming more and more important. Fortunately, there are a number of repeated modules in the H.264-IME block, thus the well-known Iterative-Logic-Array (ILA) architecture can be applied to test all the modules with constant number of test patterns. The most important condition for the ILA architecture is that the I/O function of each module should be bijective (reversible). However, most of the original designs do not have this property. In this paper, effective ILA design-for-testability schemes are proposed for both H.264-FSIME and H.264-ABIME blocks. The repeated modules are modified to be bijective and cascaded as the ILA architecture. Then each module can be fully tested by only testing the first module exhaustively. A simple built-in self-test circuit is also proposed. Moreover, the physical designs of the scan-chain and the proposed test schemes are synthesized with the UMC 0.18um technology. The total test time of the proposed method is only about 13.53% of that of scan-chain method with ATPG (Automatic Test Pattern Generation), and the hardware and delay-time overheads are still very low.