V頻段平面電路與波導之多層結構轉接設計

Abstract

本篇論文延續前人提出之兩種微帶線至基板合成波導之垂直轉接，以及一種共面波導至共面波導之覆晶垂直轉接，並將這些結構製作在低溫共燒陶瓷(low-temperature co-fired ceramic, LTCC)或RO4003基板上。論文中也同時分析轉接結構的等效電路以方便設計。 第一種轉接結構是利用微帶線末端連接一連通柱(via)至基板合成波導的底部形成短路，利用在這個連通柱上產生的電流激發電磁場至基板合成波導達成轉接。微帶線製作在基板的上層，下層則利用金屬連通柱陣列等效成波導中的垂直金屬壁，來形成基板合成波導(substrate integrated waveguide, SIW)。此結構中心頻率設計在73GHz，比例頻寬約17%，插入損耗約為0.72dB，工作頻段內(71~76GHz)之S11皆低於-15dB，符合計畫中之需求。 第二種轉接結構則是利用在基板合成波導的上板開一槽線，並且利用一終端開路的微帶線饋入，利用槽線等效出的磁流將電磁場耦合(couple)至基板合成波導來形成轉接。微帶線製作在基板的上層，下層則利用金屬連通柱陣列等效成波導中的垂直金屬壁，來形成基板合成波導(substrate integrated waveguide, SIW)。此結構中心頻率設計在73GHz，比例頻寬約38.7%，插入損耗約為1.07dB，工作頻段內(71~76GHz)之S11皆低於-15dB，符合計畫中之需求。另外，吾人將微帶線末端四分之一波長部份改成扇形(radial-shaped)，可以有效的增加其頻寬及縮短轉接部份的長度，此種結構之中心頻率設計在60GHz，比例頻寬約53.3%，插入損耗約為0.65dB，工作頻段內(57~66GHz)之S11皆低於-15dB，符合計畫中之需求。 第三種轉接結構係利用覆晶(flip-chip)之方式將兩個共面波導(coplanar waveguide, CPW)連接在一起，利用在共面波導接地端(ground)挖槽的方法做電容與電感的補償，以達到阻抗匹配進而形成轉接。此轉接設計規格從直流至25GHz，頻帶內之S11皆低於-10dB。 以上電路均使用商業軟體Ansoft HFSS來分析，包括轉接結構的反射損耗S11、插入損耗S21、輸入阻抗、以及電磁場的場型，並實際製作、實驗加以驗證。

This thesis continues previous works of two kinds of vertical transitions between microstrip line and substrate integrated waveguide (SIW), and a vertical transition between coplanar waveguides (CPW) utilizing flip-chip method. All these structures are fabricated on low-temperature co-fired ceramic (LTCC) or RO4003 substrate. This thesis also analyzes the equivalent circuits of the transition structures. The first transition design is realized with a shorted via between the end of the microstrip line and the bottom layer of SIW. A current is induced on the via and energy is coupled to SIW. The microstrip line is on the upper layer, and the SIW is on the lower layers with vertical metal walls realized by closely spaced vias. This structure is designed at 73GHz with a 17% fractional bandwidth (FBW) and a 0.72dB insertion loss. Another transition structure is realized with a slot on the top wall of SIW, which is fed by a microstrip line ended with a quarter wave length open stub. With the magnetic current induced on the slot, the transition is achieved. The microstrip line is on the upper layer, and the SIW is on the lower layers with vertical metal walls realized by closely spaced vias. This structure is designed at 73GHz with a 38.7% FBW and 1.07dB insertion loss. Another design is also given at 60GHz with a radial stub, a 53.3% FBW and 0.65dB insertion loss can be achieved. The last transition structure is composed of two CPW sections, and is connected by flip-chip method. By cutting the corner on the ground metals of both CPW sections. The capacitance or inductance in the interconnect region can be compensated to achieve impedance matching. This structure is designed from DC to 25GHz for 10dB in-band return loss. All of the designs are simulated by Ansoft HFSS and compared with measurements. Good agreements are also obtained.