奈米銅薄膜的電阻率變化

Abstract

摘要 當電子元件尺寸縮小，銅薄膜的厚度至一百奈米以下，電阻率隨厚度降低而攀升的趨勢漸趨顯著，此稱為「尺寸效應」。本論文著重討論影響「尺寸效應」的主要兩大因素：表面散射效應及晶體邊界散射效應。論文實驗的第一部份試圖將表示表面散射效應及晶體邊界散射效應的理論連結，將此二效應合併參數後可更容易討論結構與其內部電子的物理性質改變關係。 第二部分再分別比較不同材料或不同製程方式的阻抗層，對於銅薄膜的電阻率及晶體結構影響關係，最後量測試片在低溫下及退火後的電阻率及晶體結構表現，期望可以找到降低尺寸效應的方式，改善元件的效能。

Abstract As the scale of Cu interconnects reduces to sub-100nm, the drastic resistivity increases result from the decrease of Cu thickness, which is called “size effect”. This thesis focuses on the two major factors of “size effect”－ surface scattering and grain boundary scattering. The first part of the research attempts to corelate the theory of surface scattering with the theory of grain boundary scattering. By combining parameters of the two scattering effects, we can probe into the relation between the change of film structures and physical meaning of internal electrons more reliable. The second part of the research compares resistivity and microstructure of Cu thin films with barrier layers, which is made by different materials or different processes. Finally, resistivity and grain size of the samples are measured at low temperature as well as after annealing, in hopes of reducing the Cu resistivity increase and improving the integrated-circuit efficiency.