提高信賴值之LDPC 解碼節點處理器

Abstract

LDPC (Low-Density Parity-Check) code is an error-correcting code used by the advanced communication standard of the next generation. Its error correction ability can approach the Shannon limit. Sum-product is the most powerful decoding method for LDPC codes. But owing to its high complexity, so its approximation like scaling min-sum is proposed. Although the complexity of it is much less, it suffers some performance loss compared to sum-product. Thereby, in this thesis we try to propose a modified scaling min-sum algorithm. This algorithm improves the coding performance by enhancing the belief propagated conditionally during decoding process. We also propose and implement the serial hardware architecture of our proposed algorithm. The FPGA implementation result shows that our architecture only adds 4.67 % hardware cost on function unit part. Besides that, we also apply the belief enhancement idea on DORA1 to improves its performance and reduce its operation further.