請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42479完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 顧孟愷(Mong-Kai Ku) | |
| dc.contributor.author | Chi-Wei Chen | en |
| dc.contributor.author | 陳其蔚 | zh_TW |
| dc.date.accessioned | 2021-06-15T01:14:30Z | - |
| dc.date.available | 2019-08-01 | |
| dc.date.copyright | 2009-07-31 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-07-28 | |
| dc.identifier.citation | [1] R.G. Gallager, “Low-Density Parity-Check Codes,” IEEE Transactions on
Information Theory, vol. 8, no.1, pp. 21-28, Jan. 1962. [2] R. Tanner, “A Recursive Approach to Low Complexity Codes”, IEEE Trans. Information Theory, vol.27, no.5, pp. 533-547, Sep. 1981. [3] D. MacKay and R. Neal, “Near Shannon Limit Performance of Low Density Parity Check Codes,' Electronics Letters, vol. 32, pp. 1645-1646, Aug. 1996. [4] T. Richardson and R. Urbanke, “The Capacity of Low-Density Parity-Check Codes under Message-Passing Decoding,' IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 599-618, 2001. [5] S. Chung, G. Forney, T. Richardson and R. Urbanke, “On the Design of Low-Density Parity-Check Codes within 0.0045dB of the Shannon Limit,” IEEE Communications Letters, vol. 5, pp. 58-60, Feb. 2001. [6] Digital Video Broadcasting (DVB) Second Generation Framing Structure for Broadband Satellite Applications, ETSI Std. EN 302 307 v1.1.1, 2005. [7] High Throughput Extension to the 802.11 Standard, IEEE Working Draft Proposed Standard 802.11n, 2007. [8] IEEE std. 802.16e-2005, “IEEE Standard for Local and MetroPolitan Area Networks Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems,” Feb. 28th, 2006. [9] T. Richardson, M. Shokrollahi, and R. Urbanke, “Design of Capacity-Approaching Irregular Low-Density Parity-Check Codes,' IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 619-637, 2001. [10] J. Chen, R. Tanner, J. Zhang, and M. Fossorier, “Construction of Irregular LDPC Codes by Quasi-Cyclic Extension,' IEEE Transactions on Information Theory, vol. 53, no. 4, pp. 1479-1483, 2007. [11] D. J. C. MacKay, “Good Error-correcting Codes Based on Very Sparse Matrices”, IEEE Transactions on Information Theory, vol.45, no. 3, pp.399-431, Mar. 1999. [12] M. Forssorier, M. Milhaljevic and H. Imai, “Reduced Complexity Iterative Decoding of Low Density Parity Check Codes Based on Belief Propagation,” IEEE Transactions on Communications, pp. 673-680, May 1999. [13] J. Heo and K. Chugg, “Optimization of Scaling Soft Information in Iterative Decoding via Density Evolution Methods,” IEEE Transactions on Communications, vol. 53, pp. 957-961, Jun. 2005. [14] H. Song and P. Zhang, “Optimum Offset Factor of LDPC Codes,' Electronics Letters, vol. 39, no. 14, pp. 1065-1066, 2003. [15] Jinghu Chen, A. Dholakia, E. Eleftheriou, M.P.C. Fossorier and Xiao-Yu Hu, “Reduced-Complexity Decoding of LDPC Codes”, IEEE Transactions on Communications, vol.53, pp.1288-1299, Aug. 2005. [16] E. Sharon, S. Litsyn and J. Goldberger, “An Efficient Message-Passing Scheduling for LDPC Decoding,” Proc. 23rd IEEE Convention in Tel-Aviv, pp. 223-226, Sep. 2004. [17] E. Zimmermann, P. Pattisapu, P. Bora and G. Fettweis, “Reduced Complexity LDPC Decoding using Forced Convergence,” in Proc. 7th International Symposium on Wireless Personal Multimedia Communications, Sep. 2004. [18] G. Fettweis, E.Zimmermann and W.Rave, “Forced Convergence Decoding of LDPC Codes: EXIT Chart Analysis and Combination with Node Complexity Reduction Techniques,” in Proc. 11th European Wireless Conference, Apr. 2005. [19] Shu-Cheng Chou, “Design and Implementation of a Low-Power IEEE 802.16e LDPC Decoder by Utilizing Decoding Operation Reduction Algorithm”, Master Thesis, National Taiwan University, 2008. [20] Local and metropolitan area networks Part 16: Air Interface for Fixed and Mobile Broadband Wirelesss Access Systems Amendment 2: Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands and Corrigendum 1, IEEE Std. 802.16e, 2006. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42479 | - |
| dc.description.abstract | LDPC (Low-Density Parity-Check) code is an error-correcting code used by the advanced communication standard of the next generation. Its error correction ability can approach the Shannon limit. Sum-product is the most powerful decoding method for LDPC codes. But owing to its high complexity, so its approximation like scaling min-sum is proposed. Although the complexity of it is much less, it suffers some performance loss compared to sum-product. Thereby, in this thesis we try to propose a modified scaling min-sum algorithm. This algorithm improves the coding performance by enhancing the belief propagated conditionally during decoding process. We also propose and implement the serial hardware architecture of our proposed algorithm. The FPGA implementation result shows that our architecture only adds 4.67 % hardware cost on function unit part. Besides that, we also apply the belief enhancement idea on DORA1 to improves its performance and reduce its operation further. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T01:14:30Z (GMT). No. of bitstreams: 1 ntu-98-R95922110-1.pdf: 1096516 bytes, checksum: fb3494a7f77e8c13dac2713f21766610 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | 中文摘要....................................................................................................................... i
ABSTRACT ................................................................................................................. ii CONTENTS ................................................................................................................ iii LIST OF FIGURES ..................................................................................................... vi LIST OF TABLES ..................................................................................................... viii Chapter 1 Introduction.......................................................................................... 1 1.1 Overview of Channel Coding in Digital Communication System ................ 1 1.2 Overview of LDPC Codes .......................................................................... 3 1.3 Motivation .................................................................................................. 3 1.4 Thesis Organization .................................................................................... 4 Chapter 2 Backgrounds......................................................................................... 5 2.1 Representation of LDPC Codes................................................................... 5 2.1.1 Matrix Representation........................................................................ 5 2.1.2 Graph Representation ........................................................................ 6 2.1.3 Quasi-Cyclic LDPC Codes ................................................................ 7 2.2 LDPC Decoding Algorithms ....................................................................... 8 2.2.1 Sum-Product Algorithm ..................................................................... 9 2.2.2 Min-Sum Algorithm......................................................................... 13 2.2.3 Complexity Comparison .................................................................. 15 2.3 Decode Scheduling Schemes..................................................................... 16 2.3.1 Two-Phase Scheduling Scheme........................................................ 16 2.3.2 Horizontal Layered Scheduling Scheme........................................... 17 iv 2.4 Value-Reuse Property................................................................................ 20 Chapter 3 The Proposed Algorithm .................................................................... 22 3.1 Overview .................................................................................................. 22 3.1.1 Belief Enhancement for LDPC Decoding......................................... 22 3.1.2 Simulation test and Analysis ............................................................ 22 3.2 Proposed algorithm................................................................................... 28 3.3 Parameter adjustment and Simulation results ............................................ 29 3.3.1 Reliable threshold adjustment .......................................................... 30 3.3.2 Enhanced belief adjustment ............................................................. 30 3.3.3 Fianl simulation result ..................................................................... 31 3.4 Apply Belief Enhancing idea on DORA1.................................................. 32 Chapter 4 The Proposed Hardware Architecture............................................... 34 4.1 IEEE 802.16e LDPC Code Parity-Check Matrix ....................................... 34 4.2 The Decoder Architecture Overview ......................................................... 35 4.2.1 Data Path of the Decoder ................................................................. 35 4.2.2 Control Unit..................................................................................... 36 4.2.3 Decode Processing Unit ................................................................... 37 4.3 Modifications for Proposed Algorithm ...................................................... 38 4.3.1 Modification in GLCIU ................................................................... 38 Chapter 5 FPGA Implementation Results .......................................................... 40 5.1 The FPGA Design Flow............................................................................ 40 5.1.1 System Level ................................................................................... 40 5.1.2 RTL Level ....................................................................................... 42 5.1.3 FPGA Level..................................................................................... 42 5.2 FPGA Implementation Results.................................................................. 44 v Chapter 6 Conclusion and Future Works ........................................................... 46 6.1 Conclusion................................................................................................ 46 6.2 Future Works ............................................................................................ 46 REFERENCE ............................................................................................................. 47 | |
| dc.language.iso | en | |
| dc.subject | 解碼效益 | zh_TW |
| dc.subject | 解碼器 | zh_TW |
| dc.subject | 低密度奇偶校驗碼 | zh_TW |
| dc.subject | 提高信賴值 | zh_TW |
| dc.subject | belief enhancement | en |
| dc.subject | coding performance | en |
| dc.subject | decoder | en |
| dc.subject | LDPC | en |
| dc.title | 提高信賴值之LDPC 解碼節點處理器 | zh_TW |
| dc.title | A Belief Enhancement Node Processor for LDPC Decoding | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 洪士灝,林宗男,廖俊睿 | |
| dc.subject.keyword | 低密度奇偶校驗碼,解碼器,解碼效益,提高信賴值, | zh_TW |
| dc.subject.keyword | LDPC,decoder,coding performance,belief enhancement, | en |
| dc.relation.page | 49 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-07-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-98-1.pdf 未授權公開取用 | 1.07 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。