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Title: | 金氧半場效電晶體微波及毫米波之功率放大器之研究 Research of CMOS Microwave and Millimeter-wave Power Amplifier |
Authors: | Jing-Lin Kuo 郭京霖 |
Advisor: | 王暉(Huei Wang) |
Keyword: | 金氧半場效電晶體,功率放大器,K 頻帶,V 頻帶,微波單晶積體電路, CMOS,PA,K band,V band,RF amplifier,Monolithic microwave integrated circuit (MMIC), |
Publication Year : | 2008 |
Degree: | 碩士 |
Abstract: | 在本論文中,我們設計並實現了三個利用金氧半場效電晶體(CMOS)製程之功率放大器。此論文分為三個部份,第一部分介紹了在金氧半場效電晶體(CMOS)製程的功率放大器設計考量,以及一些功率放大器的基本原理。
在第二部份中,設計了第一個功率放大器使用標準0.18-微米CMOS製程,此設計的最大困難是其崩潰電壓僅為1.8 V。我們使用適當的匹配電路設計達到良好的輸出功率及小訊號增益。此功率放大器經由量測可得在24 GHz,輸出功率為19.1 dBm,小訊號增益為18.8 dB,晶片面積僅有0.56 x 0.58平方毫米。 在第三部分,我們設計並量測了兩個應用於60 GHz之系統的功率放大器。兩者皆使用薄膜微帶傳輸線作為匹配元件,以減低損耗性基板對被動元件的影響。第一個功率放大器使用0.13-微米CMOS製程,由量測結果顯示,當VDD偏壓在3V時,此功率放大器由量測可得在55 GHz,飽和輸出功率為14.3 dBm,輸出功率1-dB功率壓縮點 (P1dB)為11.2 dBm,功率附加效率(PAE)為8 %,小訊號增益為15.5 dB且面積只有0.65 x 0.5平方毫米。第二個功率放大器則使用較先進的90奈米CMOS製程。此電路設計具有寬頻的響應以增加對製程變異性的容忍度,3-dB頻寬從50-70 GHz且面積只有0.66 x 0.5平方毫米,量測結果顯示,當VDD偏壓在2.4 V時,此功率放大器由量測可得在60 GHz,飽和輸出功率為16.2 dBm,輸出功率1-dB功率壓縮點(P1dB)為12 dBm,功率附加效率(PAE)為15 %,小訊號增益為33 dB。 這三個電路皆顯示了模擬及量測的一致性,而且三者的輸出功率皆優於目前相近頻帶已發表之金氧半場效電晶體(CMOS)功率放大器,顯示出金氧半場效電晶體(CMOS)製程於高頻功率應用的潛力。 The goal of the thesis is to design and implement three power amplifiers (PAs) in CMOS process. The thesis consists of three parts. The first part introduces the basic of power amplifier theory, then introduces the design consideration and the design challenge of the CMOS power amplifier. In the second part, the first PA is implemented in a standard 0.18-μm CMOS technology. The major challenge of this circuit is that the breakdown voltage is about 1.8 V. Proper design of matching networks leads to good power and gain performances. The measured output power is 19.1 dBm and the small signal gain is 18.8 dB at 24 GHz. The chip size is only 0.56 x 0.58 mm2. In the third part, two PAs are designed and measured for 60 GHz systems. Thin-film microstrip lines (TFMS) used as matching elements to reduce the effect of lossy substrate on these two circuits. The first PA fabricated in 0.13-μm CMOS process. This PA achieves a measurement Psat of 14.3 dBm, P1dB of 11.2 dBm, PAE of 8 %, and linear gain of 15.5 dB at the frequency of 55 GHz, with a chip size of 0.66 x 0.5 mm2, when VDD is biased at 3 V. The second PA fabricated in a more advanced 90-nm CMOS process. The circuit is designed to have a wide-band frequency response to tolerate process variation. The MMIC PA has a wide 3-dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 x 0.5 mm2. When VDD is biased at 2.4 V, this PA achieves a measurement Psat of 16.2 dBm, P1dB of 12 dBm, PAE of 15 %, and linear gain of 33 dB at the frequency of 60 GHz. The simulations agree with the measurements very well in these PAs, also, three PAs demonstrated high output power compared with the previously works of CMOS PAs operating at frequencies around 24 GHz and 60 GHz. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42235 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電信工程學研究所 |
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ntu-97-1.pdf Restricted Access | 3.15 MB | Adobe PDF |
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