以FPGA實現直流/直流降壓型轉換器之PI控制與電流均流

Abstract

本論文主要探討二相交錯式同步降壓型轉換器(Dual-Phase Interleaved Synchronous Buck Converter)之數位分析與控制，以數位/類比轉換器(A/D Converter, ADC)、補償器(Compensator)與數位脈波寬度調變(Digital Pulse Width Modulator, DPWM)為數位回授之架構。其中二相交錯式同步降壓轉換器為受控體(Controlled Platform)或電源平台(Power Stage)，而補償器為輸出電壓與電感電流回授之補償，採用比例-積分(Proportional-Intergration)補償方式，電流迴路亦使用鏈控制演算法(Chain Control Algorithm)使電流均流(Current Sharing)。 主要在Matlab/Simulink環境中，使用System Generator for DSP工具進行電路建構與模擬，並使用hardware in the loop驗證，再轉成位元串流(Bitstream)，以ChipScope下載至Xilinx FPGA(Field Programmable Gate Array) - Spartan 3E；或轉成硬體描述語言(Hardware Description Language, HDL)，透過Xilinx ISE(Integrated Synthesis Environment)進行電路合成(Synthesis)、實作(Implementation)與規劃(Configuration)。其中數位/類比轉換器為1.4MHz取樣率，受控體之輸入電壓為12V，輸出電壓為1.34V，切換頻率為500KHz。由實驗觀測負載響應狀況，並分析Chain Control下之電流均流情形。

The thesis focuses on digital analysis and control of dual-phase interleaved synchronous buck converter, and the architecture of feedback is composed of A/D Converter, Compensator, and DPWM (Digital Pulse Width Modulator). The dual-phase interleaved synchronous buck converter is controlled platform or power stage, and the compensator is sensing output voltage and inductor current with PI (Proportional-Intergration) compensator, which the current loop also uses chain control algorithm to keep the current sharing. Building the circuit using the toolbox System Generator for DSP, simulating the design in Matlab/Simulink, and verifying it by hardware in the loop. Transport the design to bitstream file, and download to Xilinx FPGA (Field Programmable Gate Array) - Spartan 3E by ChipScope. Or transport the design to hardware description language (HDL) to synthesis, implementation and configuration in Xilinx ISE (Integrated Synthesis Environment). The sample rate of A/D converter is 1.4MHz, input voltage of the power stage is 12V, output voltage is 1.34V and the switching frequency is 500KHz. In experiment, focuses on load transient response, and analyses current sharing under Chain Control.