請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42093完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉志文 | |
| dc.contributor.author | Yu-Yung Huang | en |
| dc.contributor.author | 黃鈺湧 | zh_TW |
| dc.date.accessioned | 2021-06-15T00:46:17Z | - |
| dc.date.available | 2011-09-02 | |
| dc.date.copyright | 2008-09-02 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-08-26 | |
| dc.identifier.citation | [1]Y.F. Liu and P.C. Sen, 'Digital Control of Switching Power Converters,' IEEE Control Applications, pp.635-640, 2005.
[2]Simone Buso and Paolo Mattavelli, Digital Control in Power Electronics, Morgan & Claypool Publishers, 2006. [3]Aleksandar Prodic and Dragan Maksimovic, “Mixed-Signal Simulation of Digitally Controlled Switching Converters,” IEEE Computers in Power Electronics, pp.100-105, Jun., 2002. [4]A. Dolgov, B. Miao, R. Zane, and D. Maksimović, “GUI-Based Laboratory Architecture for Teaching and Research in Digital Control of SMPS,” IEEE Computers in Power Electronics, pp.236-239, Jul., 2006. [5]Intel Specification, “VRM 9.0 DC-DC Converter Design Guidelines,” April, 2002. [6]Intel Specification, “VRM 9.1 DC-DC Converter Design Guidelines,” January, 2002. [7]Intel Specification, “Voltage Regulator-Down (VRD)10.X Design Guide,” Jul. 2004. [8]Intel Specification, “Voltage Regulator-Down (VRD)11.X Design Guide,” Jul., 2005. [9]Ilya Gavrichenkov and Anna Filatova, “Meet Intel P35: Gigabyte GA-P35-DS3R Mainboard Review,” http://www.xbitlabs.com/articles/mainboards, 2007. [10]Kopo Ko, “GIGABYTE節能主機板原理分析,” http://www.hkepc.com/?id=715, 2008. [11]Simon Ang and Alejandro Oliva, Power-Switching Converters, Second Edition, Taylor & Francis Group, 2005. [12]Chun Cheung, “Multi-Phase Interleaved DC-DC Buck Converter Design Guidelines,” Intersil Technical Brief, pp.1-14, March, 2003. [13]Xu Zhang, Yang Zhang, Regan Zane, and Dragan Maksimovic, “Design and Implementation of a Wide-bandwidth Digitally Controlled 16-phase Converter,” IEEE Computers in Power Electronics, pp.106-111, July, 2006. [14]Z. Xunwei, X. Peng, and F. C. Lee, “A Novel Current-Sharing Control Technique for Low-Voltage High-Current Voltage Regulator Module Applications,” IEEE Trans. on Power Electronics, Vol.15, No.6, pp.1153-1162, Nov, 2000. [15]A. V. Peterchev, J. Xiao, and S. R. Sanders, “Architecture and IC Implementation of a Digital VRM Controller,” IEEE Trans. on Power Electronics, vol.18, no.1, pp.356-364, January 2003. [16]Y. Zhang, R. Zane, and D. Maksimovic, “Current Sharing in Digitally Controlled Masterless Multi-Phase DC-DC Converters,” Power Electronics Specialists Conference, pp.2722-2728, Jun., 2005. [17]Fang Lin Luo, Hong Ye, Muhammad Rashid, Digital Power Electronics and Applications, Academic Press, 2005. [18]Spartan-3E Starter Kit Board User Guide, Xilinx Inc., 2006. [19]Y. Zhang, R. Zane, and D. Maksimovic, “Dynamic Loop Analysis for Modular Masterless Multi-Phase DC-DC Converters,” IEEE COMPEL Workshop, pp. 22-28, June, 2006. [20]鄭群星編著，FPGA/CPLD數位晶片設計入門-使用Xilinx ISE發展系統，全華科技圖書，台北，2005。 [21]Xilinx FPGA Spartan 3E Starter Kit, http://www.fpga.synth.net/pmwiki/pmwiki.php?n=FPGASynth.Spartan3EStarterKit. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42093 | - |
| dc.description.abstract | 本論文主要探討二相交錯式同步降壓型轉換器(Dual-Phase Interleaved Synchronous Buck Converter)之數位分析與控制，以數位/類比轉換器(A/D Converter, ADC)、補償器(Compensator)與數位脈波寬度調變(Digital Pulse Width Modulator, DPWM)為數位回授之架構。其中二相交錯式同步降壓轉換器為受控體(Controlled Platform)或電源平台(Power Stage)，而補償器為輸出電壓與電感電流回授之補償，採用比例-積分(Proportional-Intergration)補償方式，電流迴路亦使用鏈控制演算法(Chain Control Algorithm)使電流均流(Current Sharing)。
主要在Matlab/Simulink環境中，使用System Generator for DSP工具進行電路建構與模擬，並使用hardware in the loop驗證，再轉成位元串流(Bitstream)，以ChipScope下載至Xilinx FPGA(Field Programmable Gate Array) - Spartan 3E；或轉成硬體描述語言(Hardware Description Language, HDL)，透過Xilinx ISE(Integrated Synthesis Environment)進行電路合成(Synthesis)、實作(Implementation)與規劃(Configuration)。其中數位/類比轉換器為1.4MHz取樣率，受控體之輸入電壓為12V，輸出電壓為1.34V，切換頻率為500KHz。由實驗觀測負載響應狀況，並分析Chain Control下之電流均流情形。 | zh_TW |
| dc.description.abstract | The thesis focuses on digital analysis and control of dual-phase interleaved synchronous buck converter, and the architecture of feedback is composed of A/D Converter, Compensator, and DPWM (Digital Pulse Width Modulator). The dual-phase interleaved synchronous buck converter is controlled platform or power stage, and the compensator is sensing output voltage and inductor current with PI (Proportional-Intergration) compensator, which the current loop also uses chain control algorithm to keep the current sharing.
Building the circuit using the toolbox System Generator for DSP, simulating the design in Matlab/Simulink, and verifying it by hardware in the loop. Transport the design to bitstream file, and download to Xilinx FPGA (Field Programmable Gate Array) - Spartan 3E by ChipScope. Or transport the design to hardware description language (HDL) to synthesis, implementation and configuration in Xilinx ISE (Integrated Synthesis Environment). The sample rate of A/D converter is 1.4MHz, input voltage of the power stage is 12V, output voltage is 1.34V and the switching frequency is 500KHz. In experiment, focuses on load transient response, and analyses current sharing under Chain Control. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T00:46:17Z (GMT). No. of bitstreams: 1 ntu-97-J95921033-1.pdf: 3374344 bytes, checksum: 1992cdba4c15dbb6e62b40fba9931341 (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 摘要.....................................i
Abstract................................ii 目錄...................................iii 圖目錄..................................iv 表目錄..................................vi 第一章 緒論..............................1 1.1 研究動機與目的.......................1 1.2 論文架構.............................2 第二章 電壓調整模組......................3 2.1 簡介.................................3 2.2 降壓型轉換器.........................5 2.3 二相式降壓型轉換器...................7 2.4 小訊號模型..........................10 2.5 電流均流(Current Sharing)...........15 2.5.1 均流介紹..........................15 2.5.2 均流與元件參數....................16 2.5.3 鏈控制(Chain Control..............20 2.6 電流感測方法........................21 2.6.1 電阻法............................21 2.6.2 導通電阻法........................22 2.6.3 DCR法.............................22 第三章 數位控制器設計...................23 3.1 數位概念............................23 3.2 功能架構............................24 3.3 類比/數位轉換器(A/D converter)......25 3.4 補償器(Compensator..................28 3.4.1 系統模型建立......................28 3.4.2 控制迴路分析......................30 3.5 數位脈波寬度調變(DPWM)..............35 第四章 模擬與實驗結果...................36 4.1 平台建構............................36 4.2 模擬電路與結果......................37 4.3 實驗平台與結果......................44 4.3.1 控制迴路分析......................44 4.3.2 實驗設備..........................45 4.3.3 實驗波形..........................46 第五章 結論與未來研究方向...............53 5.1 結論................................53 5.2 未來研究方向........................53 參考文獻................................54 | |
| dc.language.iso | zh-TW | |
| dc.subject | 比例-積分補償器 | zh_TW |
| dc.subject | 交錯式同步降壓型轉換器 | zh_TW |
| dc.subject | 數位脈波寬度調變 | zh_TW |
| dc.subject | 鏈控制 | zh_TW |
| dc.subject | 電流均流 | zh_TW |
| dc.subject | DPWM | en |
| dc.subject | PI compensator | en |
| dc.subject | Current Sharing | en |
| dc.subject | Chain Control | en |
| dc.subject | Interleaved Synchronous Buck Converter | en |
| dc.title | 以FPGA實現直流/直流降壓型轉換器之PI控制與電流均流 | zh_TW |
| dc.title | PI Control and Current Sharing of DC/DC Buck Converters Based on FPGA | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉添華,邱煌仁 | |
| dc.subject.keyword | 交錯式同步降壓型轉換器,電流均流,比例-積分補償器,數位脈波寬度調變,鏈控制, | zh_TW |
| dc.subject.keyword | Interleaved Synchronous Buck Converter,Current Sharing,PI compensator,DPWM,Chain Control, | en |
| dc.relation.page | 55 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-08-26 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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| ntu-97-1.pdf 未授權公開取用 | 3.3 MB | Adobe PDF |
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