一種適用於非同步電路之可測試設計

Abstract

本論文提出了一個適用於非同步延遲非敏感電路的掃描測試技術。本文提出的是一個真正非同步的掃描練設計，因為完全不需要任何的時脈控制，即使在測試模式下也不需要時脈控制，而是以非同步的方式來完成掃描。可達到完整掃描且測試圖樣可以組合邏輯式自動圖樣產生器來產生。在非同步的8051資料路徑的電路模擬上可以達到99.59%的高錯誤涵蓋率且相較於之前的技術只需要較少面積消耗。本文所提出的技術已在玻璃基板上的非晶矽薄膜電晶體電路晶片上實做成功。本技術對於非同步延遲非敏感電路及其相關應用電路，例如：大面積的系統晶片設計、全域非同步且區域同步的系統電路設計、軟性電子、系統整合型面板、等，提供了一個很好的掃描測試技術。

This thesis presents a scan test technique for asynchronous delay-insensitive circuits. A true asynchronous scan chain design is proposed because no clock is needed even in the test mode and scan testing can be done in asynchronous way. Full scan is available and test pattern generation can be performed by combinational automatic test pattern generation tool. Experiments on an 8051 datapath circuit show that the fault coverage is as high as 99.59% and the area overhead is smaller than previous methods. The presented idea is successfully demonstrated in two chips of a-Si TFT technology on the glass substrate. This proposed scan test technique provides a good solution for the asynchronous delay-insensitive circuit applications, such as large area system chip, globally asynchronous locally synchronous system-on-chip, flexible electronics, and system-on-panel etc.