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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
| dc.contributor.author | Po-Hsun Chiu | en |
| dc.contributor.author | 邱柏薰 | zh_TW |
| dc.date.accessioned | 2021-06-15T00:18:19Z | - |
| dc.date.available | 2010-04-09 | |
| dc.date.copyright | 2009-04-09 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-03-30 | |
| dc.identifier.citation | References
________________________________________ [1] T. Nagano, H. Kageyama, H. Akimoto, Y. Mikami, and H. Sato, “A 5-Inch SVGA Low-Temperature Poly-Si TFT-LCD with Integrated Digital Interface Driver,” In International Conference on Solid-State and Integrated-Circuit Technology, Vol. 2, pp. 22-25, 2001. [2] T. Nakamura, M. Karube, H. Hayashi, K. Nakamura, N. Tada, H. Fujiwara, J. Tsutsumi, and T. Motai, “Low-Temperature Poly-Si TFT-LCD with an Integrated Analog Circuit,” Journal of the Society for Information Display, Vol. 10(3), pp. 203-207, 2002. [3] Y. S. Yoo, J. Y. Choi, H. S. Shim, and O. K. Kwon, “A High Accurate Analog Buffer Circuit Using Low Temperature Poly-Si TFT,” Digest of the Society for information display, Vol. 35(1), pp. 1460-1463, 2004. [4] C. W. Lin, T. K. Chang, C. K. Jan, M. H. Hsieh, C. Y. Tsai, S. C. Chang, and Y. M. Tsai, “LTPS Circuit Integration for System-on-Glass LCDs,” Journal of the Society for Information Display, Vol. 14(4), pp. 353-362, 2006. [5] H. Haga, H. Tsuchi, K. Abe, N. Ikeda, H. Asada, H. Hayama, K. Shiota, and N. Takata, “A Parallel Digital-Data-Driver Architecture for Low-Power Poly-Si TFT LCDs,” Digest of the Society for information display, 690-693, 2002. [6] S. H. Jung, W. J. Nam, C. W. Han, and M. K. Han, “A New Low Power PMOS Poly-Si Inverter and Driving Circuits for Active-Matrix Displays,” Digest of the Society for information display, 1396-1399, 2003. [7] Y. Matsueda, R. Kakkad, Y. S. Park, H. H. Yoon, W. P. Lee, J. B. Koo, and H. K. Chung, “2.5-in. AMOLED with Integrated 6-Bit Gamma Compensated Digital Data Driver,” Digest of the Society for information display, 1116-1119, 2004. [8] B. S. Bae, J. W. Choi, J. H. Oh, and J. Jang, “Level Shift Embedded in Drive Circuits with Amorphous Silicon TFTs,” IEEE Transactions on Electron Devices. Vol. 53(3), 494-498, 2006. [9] W. K. Lee, J. H. Lee, H. S. Park, W. C. Lee, Y. B. Jung, and M. K. Han, “Low-Power a-Si:H Level shift for Mobile Displays with Bootstrapped Capacitor and Pulsed Signal Source,” Digest of the Society for information display,, Vol. 38(1) 218-221, 2007. [10] K. R. Wissmiller, J. E. Knudsen, T. J. Alward, Z. P. Li, D. R. Allee, L. T. Clark, “Reducing Power in Flexible a-Si:H Digital Circuits While Preserving State,” Proc Custom Integrated Circuits Conference, 219–222, 2005. [11] W. Lu, “Flat Panel Display Drive Circuits,” M.S. thesis, Dept. Elect. Eng., Arizona State Univ., Tempe, AZ, 1990. [12] P. C. Hsieh, J. S. Jhuang, and T. D. Chiueh, “Design of a Low-Power, Delay Line Using Gated-Driver Tree,” Proc. of the 15th VLSI Design/CAD Symposium, Kenting, Taiwan, Aug, 2004. [13] M. L. Liou, and T. D. Chiueh, “A Low-Power Digital Matched Filter for Direct-Sequence Spread Spectrum Signal Acquisition,” IEEE Journal of Solid-State Circuits, Vol. 36(6), 933-943, 2001. [14] N. Shibata, M. Watanabe, and Y. Tanabe, “A Current-Sensed High-Speed and Low-Power First-In-First-Out Memory Using a Wordline/ Bitline-Swapped Dual-Port SRAM Cell,” IEEE Journal of Solid-State Circuits, Vol. 37(6), 2002. [15] F. M. Shams, J. Ebergen, and M. Elmasry, 'Modeling and Comparing CMOS Implementations of the C-Element,” Dep. Computer Science, Univ. of Waterloo, Waterloo, Ont., Canada, Tech. Rep. CS-98-12, 1998. [16] R. Hossain, L. D. Wronski, and A. Albicki, “Low Power Design Using Double Edge Triggered Flip-Flops,” IEEE Trans. on VLSI Systems, Vol. 2(2), 261-265, 1994. [17] T. C. Huang, and K. T. Cheng, 'Design for Printability for Flexible Electronics: Self-Tunable Cell-Library Design,” International Symposium for Flexible Electronics and Displays (ISFED), 2007. [18] K. S. Karim, A. Nathan, M. Hack, and W. I. Milne, “Drain-Bias Dependence of Threshold Voltage of Amorphous Silicon TFTs,” IEEE Electron Device Letters. Vol. 25(4), 188-190, 2004. [19] K. Long, I. C. Cheng, A. Kattamis, H. Gleskova, S. Wagner, and J. C. Sturm, “Amorphous-Silicon Thin-Film Transistors Made at 280°C on Clear-Plastic Substrates by Interfacial Stress Engineering,” Journal of the Society for Information Display, Vol. 15(3), 167-176, 2007. [20] K. Miwa, Y. Maekawa, and T. Tsujimura, “Modeling of Threshold Voltage Shift Dependency on Drain Bias in Amorphous Silicon Thin Film Transistors in Active-Matrix Organic Light-Emitting-Diode Displays,” Journal of the Society for Information Display, Vol. 15(12), 1131-1136, 2007. [21] H. Lebrun, N. Szydlo, and E. Bidal, “Threshold-voltage Drift of Amorphous-Silicon TFTs in Integrated Drivers for Active-Matrix LCDs,” Journal of the Society for Information Display, Vol. 11(3), 539-542, 2003. [22] F. Maurice, H. Lebrun, N. Szydlo, U. Rossini, and R. Chaudet, “High Resolution Projection Valve with the Amorphous Silicon AMLCD Technology,” IS&T/SPIE Conference on Projection Displays IV, 92-99, 1998. [23] M. Shams, J. Ebergen, and M. Elmasry, “Modeling and Comparing CMOS Implementations of the C-Element,” Dept. Computer Science, Univ. of Waterloo, Waterloo, Ont., Canada, Tech. Rep. CS-98-12, 1998. [24] C. H. Kim, S. J. Yoo, H. J. Kim, J. M. Jun, and J. Y. Lee, 'Integrated a-Si:H TFT Row Driver Circuits for High-Resolution Applications,” Journal of the Society for Information Display, Vol. 14(4), 333-337, 2006. [25] Sang-Hoon Jung, Woo-Jin Nam, Chang-Wook Han, and Min-Koo Han, “A New Low Power PMOS Poly-Si Inverter and Driving Circuits for Active Matrix Displays,” Digest of the Society for information display, Vol. 34(3), 1396-1399, 2003. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/41404 | - |
| dc.description.abstract | 隨著顯示技術的發展與消費需求的增加，輕、薄、短、小跟低功率已經變成現在顯示器的兩大發展趨勢。其中一個縮小面積的方法是將周邊的閘極驅動器整合在面板上。在這篇論文中，我們提出了一個針對這種方法的低功耗閘極驅動器電路。這種電路設計可以大幅的降低功率消耗並且幫助穩定浮動閘線。 | zh_TW |
| dc.description.abstract | With the recent advance in display technology and consumer demands, compact form factor and low power consumption has become the trend of modern displays. One popular approach to reduce the form factor is to integrate the gate drivers on the same glass as the display. In this thesis, we propose a low power gate driver design for such displays. It not only substantially lowers the power consumption but also help stabilize the floating gate lines. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T00:18:19Z (GMT). No. of bitstreams: 1 ntu-98-R95943102-1.pdf: 1876078 bytes, checksum: fd5f34f1f279b2009eaa26dddf7ad1e9 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | Contents
________________________________________ 誌謝 I 摘要 II Abstract III Contents IV Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Contribution 5 1.3 Thesis Structure 6 Chapter 2 Preliminaries 7 2.1 TFT-LCD Driving Circuitry 7 2.1.1 Data Driver 7 2.1.2 Scan Driver 10 2.2 Low Power Circuit Design 13 2.2.1 Low Power Level Shift with Pulse Source and Bootstrapped Capacitor 13 2.2.2 Reducing Power in Flexible a-Si:H Digital Circuits While Preserving State 17 2.2.1 The Clock-Gated Ring Counter 21 Chapter 3 The Proposed Techniques 27 3.1 A-Si:H TFT Gate Driver Architecture 27 3.2 The Clock-Gating Circuit 31 3.2.1 The C-element 31 3.2.2 Switches 34 3.3 Power Reduction Estimation 35 Chapter 4 Simulation Results 39 4.1 The Clock-Gating Circuit 39 4.2 The Gate Driver Output 41 4.3 The Floating Gate-Line Fluctuation Attenuation 43 4.4 Power Reduction 47 4.5 Area overhead 49 Chapter 5 Experimental Result 51 5.1 The Clock-Gating Circuit 53 5.1.1 Inverter 53 5.2 The Gate-Line and Gate Driver Output 57 5.3 Short Circuits Test 59 5.4 Summary of Experimental Result 60 Chapter 6 Conclusion and Further Work 63 6.1 Conclusion 63 6.2 Further Work 63 References 64 | |
| dc.language.iso | en | |
| dc.subject | 閘極驅動器 | zh_TW |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 浮動閘線 | zh_TW |
| dc.subject | low power | en |
| dc.subject | floating gate line | en |
| dc.subject | gate drivers | en |
| dc.title | 可降低功率消耗與穩定浮動閘線的非晶矽閘極驅動電路設計 | zh_TW |
| dc.title | A Segmented a-Si Gate Driver Design for Power Reduction and Floating Gate Line Stabilization | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李建模(Chien-Mo Li),呂良鴻(Liang-Hung Lu) | |
| dc.subject.keyword | 閘極驅動器,低功率,浮動閘線, | zh_TW |
| dc.subject.keyword | gate drivers,low power,floating gate line, | en |
| dc.relation.page | 66 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-03-31 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-98-1.pdf 未授權公開取用 | 1.83 MB | Adobe PDF |
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