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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/41174完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文(Yao-Wen Chang) | |
| dc.contributor.author | Ya-Ching Lee | en |
| dc.contributor.author | 李雅菁 | zh_TW |
| dc.date.accessioned | 2021-06-14T17:21:43Z | - |
| dc.date.available | 2011-07-30 | |
| dc.date.copyright | 2008-07-30 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-07-24 | |
| dc.identifier.citation | [1] M. Anis, S. Areibi and M. Elmasry, “Design and optimization of multi-threshold CMOS (MTCMOS) circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 10, October 2003.
[2] B. H. Calhoun, F. A. Honore and A. P. Chandrakasan, “A leakage reduction methodology for distributed MTCMOS”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 5, May 2004. [3] R. Chaudhry, D. Blauw, R. Panda and T. Edwards, “Current signature compression for IR-Drop analysis”, in Proceedings of ACM/IEEE Design Automation Conference, pp. 162-167, June 2000. [4] A. Dharchoudhury, R. Panda, D. Blaauw, R. Vaidyanathan, B. Tutuianu, and D. Bearden, “Design and analysis of power distribution networks in PowerPCTM microprocessors,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 738-743, Jun 1998. [5] F. Hamzaoglu and M. R. Stan, “Circuit-level techniques to control gate leakage for sub-100nm CMOS”, in Proceedings of International Symposium on Low Power Electronics and Design, pp. 60-63, August 2002. [6] J. Kao, A. Chandrakasan and D. Antoniadis, “Transistor sizing issues and tool for multi-threshold CMOS technology”, in Proceedings of ACM/IEEE Design Automation Conference, pp. 409-414, June 1997. [7] J. Kao, S. Narendra and A. Chandrakasan, “MTCMOS hierarchical sizing based on mutual exclusive discharge patterns”, in Proceedings of ACM/IEEE Design Automation Conference, pp. 495-500, June 1998. [8] D. Lee, D. Blaauw, and D. Sylvester, “Gate oxide leakage current analysis and reduction for VLSI circuits”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 12, No. 2, pp. 155-166, February 2004. [9] S. Lin and N. Chang, “Challenges in power-ground integrity”, in Proceedings of International of Conference of Computer Design, pp. 651-654, November 2001. [10] C.-W. Liu, Y.-W. Chang, “Power/Ground network and floorplan cosynthesis for fast design convergence,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 4, pp. 693-704, April 2007. [11] C. Long and L. He, “Distributed sleep transistor network for power reduction”, in Proceedings of ACM/IEEE Design Automation Conference, pp. 181-186, June 2003. [12] C. Long, J. Xiong and L. He, “On optimal physical synthesis of sleep transistors, in Proceedings of ACM International Symposium on Physical Design, pp. 156-161, April 2004. [13] M. Powell, S.-H Yang, B. Falsafi, K. Roy and T. N. Vijaykumar, “Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories”, in Proceedings of International Symposium on Low Power Electronics and Design, pp. 90-95, July 2000. [14] A. Ramalingam, B. Zhang, A. Davgan and D. Pan, “Sleep transistor sizing using timing criticality and temporal currents”, in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference, pp. 1094-1097, January 2005. [15] K. Roy, S. Mukhopadhyay, and H. Mahmoodimeimand, “Leakage current mechanism and leakage reduction techniques in deep-submicrometer CMOS circuits”, in Proceedings of the IEEE, Vol. 91, No. 2, pp. 305-327, February 2003. [16] K. Shi and D. Howard, “Challenges in sleep transistor design and implementation in low-power designs,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 113-116, July 2006. [17] K. Shi, Z. Lin and Y.-M. Jiang, “A power network synthesis method for industrial power gating designs,” in Proceedings of the 8th International Symposium on Quality Electronic Design, pp. 362-367, March 2007. [18] S. Shigematsu, S. Mutoh, Y. MATSYUA and J. YAMADA, “A 1-V high-speed MTCOMS circuit scheme for power-down application circuits”, IEEE Journal of Solid-State Circuits, Vol. 32, No. 6, pp. 861-869, June 1997. [19] X. Tan, C.-J. R. Shi, “Fast power/ground network optimization based on equivalent circuit modeling,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 550-554, June 2001. [20] S. X.-D. Tan, C.-J. R. Shi and J.-C. Lee, “Reliability-constrainted area optimization of VLSI power/ground networks via sequence of linear programmings,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, NO. 12, pp. 1678-1684, December 2003. [21] S.-W. Wu and Y.-W. Chang, “Efficient power/ground network analysis for power integrity-driven design methodlogy,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 177-180, June 2004. [22] J.-S. Yim, S-O. Bae, and C.-M. Kyung, “A floorplan-based planning methodology for power and clock distribution is ASICs,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 766-771, June 1999. [23] PNA –Synopsys power network analysis manual. [24] IC Compiler – Synopsys IC Compiler manual. [25] R. J. Baker, H. W. Li and D. E. Boyce, “CMOS circuit design, layout, and simulation,” IEEE Press, 1997. ISBN: 0-7803-3416-7. [26] Q. K. ZHU, “Power distribution network design for VLSI,” Wiley, February 2004. ISBN 0-471-65720-4. [27] M. Keating, D. Flynn, R. Aitken, A. Gibbons and K. Shi, “Low power methodology manual for system-on-chip design,” Springer, 2007. ISBN: 978-0-387-71818-7. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/41174 | - |
| dc.description.abstract | 在先進製程中，電晶體開關(sleep transistor)是一個可以有效降低靜態和動態功率消耗的方法。然而，因為電晶體開關的加入，也會衍生出晶片面積增大、繞線空間減少、電源網路的電壓降增加和電路複雜度增加等問題。為了有效地增加電晶體開關使用的效率，我們提出一套方法，可以快速的調整出一個最佳的電晶體電源網路，讓電源網路的電壓降可以符合要求且可以減少電晶體開關和電源網路的使用面積而增加繞線空間。我們使用兩個設計案例去證實所提出來的方法和流程，結果顯示這個方法確實可以快速的調整出一個最佳的電晶體電源網路和計算出電源網路的電壓降(IR drop)，在電源網路的電壓降可以符合要求的前提下使用較少的電晶體電源網路去提升繞線空間。 | zh_TW |
| dc.description.abstract | Using sleep transistors to implement the power-gating design is an effective method for reducing dynamic and leakage power in advanced process. However, sleep transistors will encourage extra cost in chip area, reduce routing resource, and increase IR drop and design complexity. Although a denser power network can reduce IR drop, it wastes much routing area. In order to utilize this power-gating technology more efficiently, we propose a post-placement sleep transistor power network optimization method. This method can adjust the power network to meet an expected IR drop and consume smaller power network area. Two test cases are used to verify the both proposed method and design flow. Experimental results show that the proposed post-placement design flow can get accurate IR drop quickly. Furthermore, the proposed Power/Ground network adjustment methodology can also reduce 7.6% and 37.13% Power/Ground area in design 1 and design 2, respectively. So the proposed method can release more space for routing. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-14T17:21:43Z (GMT). No. of bitstreams: 1 ntu-97-P93943006-1.pdf: 1096019 bytes, checksum: 8231aafd709ac68ab782bd17e8c1f36e (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | Abstract iii
List of Tables vi List of Figures vii Chapter 1 Introduction…………………………………………..…………….1 1.1 Related Previous Work…………………………………...……………..1 1.1.1 Power Network Design……………………………………………....1 1.1.2 Sleep Transistors Implementation………………….……………....5 1.1.3 Power-gating Power/Ground Network Design…...….…………….6 1.2 Our Contributions……………………………………………….……..12 1.3 Organization of the Thesis……………………………………………..13 Chapter 2 Problem Formulation …………………………………...……...…14 2.1 Distributed Sleep Transistor Network …...…………………...……….14 2.2 Distributed Sleep Transistor Power Network Model….……..…..……15 2.3 Sleep Transistor Placement Style...……………………………………16 2.4 Rail vs. Strap VDD Supply Distribution…...………………….………18 2.4.1 Parallel Rail VDD Distribution …………...……………….………18 2.4.2 Power Strap VDD Distribution…………………………….………20 2.5 Problem Formulation………………………………………….………21 2.5.1 The IR-drop Constraints…………………………………....………21 2.5.2 The Minimum Width Constraints………………………….………21 2.5.3 The Electromigration Constraints………………………….………22 2.5.4 The Sleep Transistor Layout Constraints………………………..…22 Chapter 3 Design Flow …………………...…………………...…………..…24 3.1 Typical Design Flow…………………………………………………..24 3.2 Proposed Design Flow……………………………………...…………25 Chapter 4 Experimental Results and Discussions………………...…………30 Chapter 5 Conclusion and Future Work………………………………...……38 5.1 Conclusions………………………………………………………….38 5.2 Future Work………………………………………………..…….……39 Bibliography………………………………………………………………..40 | |
| dc.language.iso | en | |
| dc.subject | 電源網路 | zh_TW |
| dc.subject | 電源開關 | zh_TW |
| dc.subject | Power-Gating | en |
| dc.subject | Power Network | en |
| dc.title | 用於電源開關設計中之元件佈置後的電源網路最佳化方法 | zh_TW |
| dc.title | Post-Placement Power Network Optimization for Power-Gating Design | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林榮彬(Rung-Bin Lin),阮聖彰(Shang-Jang Ruan) | |
| dc.subject.keyword | 電源開關,電源網路, | zh_TW |
| dc.subject.keyword | Power Network,Power-Gating, | en |
| dc.relation.page | 43 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-07-26 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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