以電壓比較放大器為基礎之低功率內容可定址記憶體設計

Abstract

本論文發表一個新的低功率內容可定址記憶體架構設計，以電壓比較放大器為基礎，此設計可以改變命中線上的比較電壓，此外，藉由降低複製命中線的內容可定址記憶體數目，我們可以達到降低各命中線的電壓；而低電壓就代表著低功率，進而達成降低功率的目標。 此設計為256字列 X 144位元的三元內容可定址記憶體，使用1.8伏特，0.18微米製程。模擬顯示，在相同的搜尋時間下，可以減少30%的功率消耗；而在相同的電流源下，可以在搜尋時間上改進25%的時間。

This thesis presents a novel architecture for content-addressable memory with low power feature. This design is based on a proposed voltage compared match line sense amplifier that changes the comparison voltage of CAM word circuit. According to reducing cells on dummy word, we can reach low voltage on each match line and reduces power dissipation of the CAM system. The design was implemented in a 256-word X 144-bit ternary CAM for 1.8V 0.18-um CMOS process. Simulation results show that, for the same search time on TCAM match line, about 30% power reduction can be achieved and for the same current source on TCAM match line, about 25% speed reduction can be achieved.