請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/40825完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 賴飛羆 | |
| dc.contributor.author | Yi-Shun Yang | en |
| dc.contributor.author | 楊奕順 | zh_TW |
| dc.date.accessioned | 2021-06-14T17:02:08Z | - |
| dc.date.available | 2016-07-28 | |
| dc.date.copyright | 2008-08-04 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-07-28 | |
| dc.identifier.citation | [1] A. R. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design. Kluwer Academic Publishers, Norwell, MA, 1995.
[2] A. Bellaouar and M. I. Elmasry, Low-Power Digital VLSI Design – Circuits and Systems. Kluwer Academic Publishers, Norwell, MA, 1995. [3] F. Shafai, K.J. Schult, G. F.R. Gibson, A.G. Bluschke, and D.E. Somppi “Fully parallel 30-MHz, 2.5-Mb CAM”, IEEE Journal of Solid-State Circuits, vol. 33, no. 11, pp.1690-1696, Nov.1998. [4] C.A. Zukowski and Shao-Yi Wang, “Use of selective precharge for low-power content-addressable memories”, in Proc. IEEE Int. Symp. Circuits and Systems, June 1997, pp. 1788-1791. [5] H. Miyatake, M. Tanaka, and Y. Mori,” A design for high-speed low-power CMOS fully parallel content-addressable memory macros”, IEEE Journal of Solid-State Circuits, vol. 36, no. 6, pp. 956 – 968, June 2001. [6] C.-S. Lin, J.-C. Chang, and B.-D. Liu, “A low-power precomputation-based fully parallel content-addressable memory”, IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp.654-662, Apr. 2003. [7] I. Arsovski, T. Chandler, and A. Sheikholeslami, “A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme”, IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp. 155 – 158, Jan. 2003. [8] G. Kasai, Y. Takarabe, K. Furumi, and M. Yoneda “200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme”, in Proc. IEEE Custom Integrated Circuits Conference, Sept. 2003, pp. 387 – 390. [9] I. Arsovski and A. Sheikholeslami, “A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories”, IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp.1958-1966, Nov. 2003. [10] S. Jones, “Design, selection and implementation of a content-addressable memory for a VLSI CMOS chip architecture”, in Proc. IEEE Computers and Digital Techniques, vol. 135, no. 3, pp. 165 – 172, May 1988. [11] F. Shafai, K.J. Schultz, G.F.R. Gibson, A. G. Bluschke, D.E. Somppi, ”Fully Parallel 30-MHz 2.5-Mb CAM,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 11, Nov. 1998, pp. 1690-1696. [12] K. Noda, K. Matsui, K. Tokashiki, K. Takeda, and N. Nakamura, “A loadless CMOS four-transistor SRAM cell in a 0.18-_m logic technology,” IEEE Trans. Electron. Devices, vol. 48, pp. 2851–2855, Dec. 2001. [13] P. Lin, J. Kuo, 'A I-V 128-kb Four-Way Set-Associative CMOS Cache Memory Using Wordline-Oriented Tag-Compare (WLOTC) Structure with the Content-Addressable-Memory(CAM) 10-Transistor Tag Cell,' IEEE J. Solid State Circuits, Vo1.36, N0.4, pp.666-676, Apr. 2001. [14] Y.-L. Hsiao, D.-H. Wang, and C.-W. Jen, “Power modeling and low-power design of content addressable memories”, in Proc. IEEE Int. Symp. Circuits and Systems,May 2001, pp. 926 – 929. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/40825 | - |
| dc.description.abstract | 本論文發表一個新的低功率內容可定址記憶體架構設計，以電壓比較放大器為基礎，此設計可以改變命中線上的比較電壓，此外，藉由降低複製命中線的內容可定址記憶體數目，我們可以達到降低各命中線的電壓；而低電壓就代表著低功率，進而達成降低功率的目標。
此設計為256字列 X 144位元的三元內容可定址記憶體，使用1.8伏特，0.18微米製程。模擬顯示，在相同的搜尋時間下，可以減少30%的功率消耗；而在相同的電流源下，可以在搜尋時間上改進25%的時間。 | zh_TW |
| dc.description.abstract | This thesis presents a novel architecture for content-addressable memory with low power feature. This design is based on a proposed voltage compared match line sense amplifier that changes the comparison voltage of CAM word circuit. According to reducing cells on dummy word, we can reach low voltage on each match line and reduces power dissipation of the CAM system.
The design was implemented in a 256-word X 144-bit ternary CAM for 1.8V 0.18-um CMOS process. Simulation results show that, for the same search time on TCAM match line, about 30% power reduction can be achieved and for the same current source on TCAM match line, about 25% speed reduction can be achieved. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-14T17:02:08Z (GMT). No. of bitstreams: 1 ntu-97-J95921013-1.pdf: 962341 bytes, checksum: 8cb4ae1a7c7450165fe008df836dcaf4 (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii LIST OF TABLES ix Chapter 1 Introduction 1 1.1 The Trend of Low Power 1 1.2 Power Dissipation of CMOS Circuit 2 1.2.1 Dynamic power 2 1.2.2 Short circuit power 3 1.2.3 Leakage power 3 1.2.4 Static power 4 1.3 Motivation 4 1.4 Previous Work 6 1.5 Thesis Organization 7 Chapter 2 Overview of CAMs 8 2.1 Typical CAM Architecture 8 2.2 Conventional 9T CAM 11 2.2.1 NOR-type 9T CAM 14 2.2.2 NAND-type 9T CAM 15 2.3 Ternary CAM 16 2.3.1 4T cell in TCAM 18 2.4 Summary 20 Chapter 3 Low Power Methodologies of Match Lins 21 3.1 Charge Injection Match Line Detect Circuits (CI-MLDC) 21 3.1.1 Search Operations of CI-MLDC 22 3.1.2 Power Reduction of CI-MLDC 23 3.1.3 Offset SA adopted of CI-MLDC 23 3.1.4 Offset and Match Line Voltage vs. Vdd 24 3.1.5 Conclusion of CI-MLDC 26 3.2 Current Race Match Line Sense Amplifier (CR-MLSA) 26 3.2.1 Operation of CR-MLSA 26 3.2.2 Voltage development of ML with a match (ML0) against a ML with a one-bit miss (ML1) 29 3.2.3 Power reduction of CR-MLSA 30 3.2.4 Conclusion of CR-MLSA 31 Chapter 4 Voltage Compared Design Techniques for Match-Line Sense Amplifier 32 4.1 Problem Description 32 4.2 The Proposed Voltage Compared Match Line Sense Amplifier Circuit 34 4.2.1 Operation Principle 36 4.2.2 Detailed Circuit for TCAM cell 37 4.2.3 Detailed Circuit for Voltage Compared MLSA 37 4.3 Simulation Results and Analysis 39 4.3.1 Simulation Results of Current Race MLSA scheme 39 4.3.2 Simulation Results of Voltage Compared MLSA scheme (the Same Search Time) 40 4.3.3 Simulation Results of Voltage Compared MLSA scheme (the Same Current Source) 42 4.3.4 Energy Comparison of Two MLSA Schemes 44 4.4 Summary 47 Chapter 5 Conclusion 48 5.1 Conclusion 48 REFERENCE 50 | |
| dc.language.iso | zh-TW | |
| dc.subject | 內容可定址記憶體 | zh_TW |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 命中線 | zh_TW |
| dc.subject | Match line | en |
| dc.subject | Low power | en |
| dc.subject | Content-addressable memory | en |
| dc.title | 以電壓比較放大器為基礎之低功率內容可定址記憶體設計 | zh_TW |
| dc.title | Design of Low Power Content Addressable Memory Based on Voltage Compared Match Line Sense Amplifier | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張延任,李鴻璋,林正偉,蔡坤霖 | |
| dc.subject.keyword | 低功率,命中線,內容可定址記憶體, | zh_TW |
| dc.subject.keyword | Low power,Match line,Content-addressable memory, | en |
| dc.relation.page | 50 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-07-30 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-97-1.pdf 未授權公開取用 | 939.79 kB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。