三維積體電路中直通矽晶穿孔的特性分析與電源完整性的應用

Abstract

近年來隨著積體電路的快速發展，在高速電路系統中高密度的晶片封裝技術正面臨巨大的挑戰，而三維積體電路中的直通矽晶穿孔技術是被視為能夠有效解決電路路徑過長、高損耗、高密度等問題的連接垂直堆疊晶片的新科技。這篇論文的核心即為直通矽晶穿孔的相關基本特性分析與其應用。 直通矽晶穿孔結構最大的特色是金屬外圍的絕緣層。該絕緣層在電性上的特性與同軸傳輸線等效電路中的電容特性極為類似，因此在分析直通矽晶穿孔時可以將同軸傳輸線的電容的特性套用在電路模型當中。直通矽晶穿孔外圍的絕緣層所產生的影響相當廣泛，如在低頻率時的低損耗特性、慢波模態現象、特徵阻抗與電場的分布等等皆是由絕緣層電容所造成的。在實際的電路中，直通矽晶穿孔的數目通常多達上千個，因此在這篇論文中除了直通矽晶穿孔的基本特性之外，也會針對眾多直通矽晶穿孔的系統，利用多導體傳輸線的等效電路模型建構出能用來表示由多個直通矽晶穿孔系統的等效電路模型。 在印刷電路板中，電磁能隙結構已經被證實可以有效降低同步切換雜訊。電磁能隙的結構除了可以應用在印刷電路板中，也可以將相同的概念設計在晶片內部的電源網格中來實現降低晶片內部雜訊的功效，因此本論文會提供如何在晶片中設計電磁能隙結構的創新想法來達到抑制雜訊的效果。

With the fast development of the integrated circuit, the techniques for packaging high-density chips in advanced high-speed system have hit the wall recently. Therefore, how to keep conforming to the Moore’s Law in 2D packaging is becoming more and more critical, and that’s why the technique involving 3D technology emerges. Among all of the possible solutions for 3D IC, through silicon via (TSV) is the most promising one in the future because it can effectively solve the issues like long interconnection path, high power consumption, and high I/O pin density. It is the basic electrical properties and application of TSV that constitute this thesis. The most significant feature of TSV is the layer of dielectric surrounding the inner conductor of TSV. This dielectric layer can be characterized with the capacitance of coaxial transmission lines, which has considerable impacts like the low-loss behavior at low frequencies, slow-wave mode, characteristic impedance, and the electric field distribution. In addition to the fundamental characteristics of TSV, the equivalent circuit model of a system containing multiple TSVs will also be investigated. In printed circuit boards (PCB), the electromagnetic bandgap (EBG) structure has been proved to be an effective solution of suppressing the simultaneous switching noise (SSN). Besides the application to PCB, EBG structure can also be implemented inside the power/ground grid within chips to isolate noise. The innovative concepts of designing the EBG structure in chips will be presented in this thesis.