使用降低解碼運算數目演算法之低功率IEEE 802.16e LDPC 硬體解碼器之設計與實現

Abstract

由於在行動應用裝置中低功率設計的需求愈來愈重要，我們提出了一個降低運算數目的LDPC解碼器演算法。這個演算法能夠減少必須運算的位元節點數目來減少功率消耗，並且在特定的解碼回數中會喚醒所有的節點來更新訊息以將位元錯誤率減至最低。除此之外，我們也研究了兩種更低硬體成本的衍生演算法，針對這三種演算法我們都提出了低成本的硬體架構。而模擬結果中顯示我們的演算法相較於原本的演算法最多可以減少75%最耗電的記憶體存取。而FPGA的實作結果顯示我們只增加了0.6%的硬體成本，並且在頻率140MHz時可以達到67~292Mbps的效能。

For the emergency of low power consumption demand in mobile applications, a decoding operation reduction algorithm for Low-Density Parity Check (LDPC) codes is proposed. Our operation reduction layered decoding algorithm reduces active node computation to lower LDPC decoder power consumption. Layered nodes are periodically refreshed to minimize coding gain degradation. Besides, two variation algorithms are also explored. Low hardware overhead partially parallel LDPC decoder architecture for all three decoding operation reduction algorithms is also described. Simulation results show that our algorithm reduces the number the most power consuming memory access operation up to 75% compared to the original layered decoding. The FPGA implementation results show that our architecture only add 0.6% hardware cost and the throughput is up to 67~292Mbps at frequency 140MHz.