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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 顧孟愷(Mong-Kai Ku) | |
| dc.contributor.author | Shu-Cheng Chou | en |
| dc.contributor.author | 周書正 | zh_TW |
| dc.date.accessioned | 2021-06-14T16:41:52Z | - |
| dc.date.available | 2013-08-08 | |
| dc.date.copyright | 2008-08-08 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-07-31 | |
| dc.identifier.citation | [1] R.G. Gallager, “Low-Density Parity-Check Codes,” IEEE Transactions on Information Theory, vol. 8, pp. 21-28, Jan. 1962.
[2] R. Tanner,“A Recursive Approach to Low Complexity Codes”, IEEE Trans. Information Theory, pp. 533-547, Sep. 1981. [3] D. MacKay and R. Neal, “Good codes based on very sparse matrices,” in Cryptography and Coding, 5th IMA Conf., pp. 100-111, Springer, 1995. [4] D. MacKay and R. Neal, “Near Shannon Limit Performance of Low Density Parity Check Codes,' Electronics Letters, vol. 33, no. 6, pp. 457-458, 1997. [5] T. Richardson and R. Urbanke, “The Capacity of Low-Density Parity-Check Codes under Message-Passing Decoding,' IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 599-618, 2001. [6] S. Chung, G. Forney, T. Richardson and R. Urbanke, “On the Design of Low-Density Parity-Check Codes within 0.0045dB of the Shannon Limit,” IEEE Communications Letters, vol. 5, pp. 58-60, Feb. 2001. [7] Digital Video Broadcasting (DVB) Second Generation Framing Structure for Broadband Satellite Applications, ETSI Std. EN 302 307 v1.1.1, 2005. [8] High Throughput Extension to the 802.11 Standard, IEEE Working Draft Proposed Standard 802.11n, 2007. [9] IEEE std. 802.16e-2005, “IEEE Standard for Local and MetroPolitan Area Networks Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems,” Feb. 28th, 2006. [10] A. Chandrakasan, S. Sheng and R. Brodersen, “Low-Power CMOS Digital Design”, IEEE Journal of Solid-State Circuits, vol. 27, no. 4, Apr. 1992. [11] Y. Kou, S. Lin, and M. Fossorier, “Low-Density Parity-Check Codes Based on Finite Geometries: Arediscovery and New Results,' IEEE Transactions on Information Theory, vol. 47, no. 7, pp. 2711-2736, 2001. [12] T. Richardson, M. Shokrollahi, and R. Urbanke, “Design of Capacity-Approaching Irregular Low-Density Parity-Check Codes,' IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 619-637, 2001. [13] H. Zhong and T. Zhang, “Design of VLSI Implementation LDPC Codes,” in Proc. IEEE 58th Vehicular Technology Conference, vol. 1, pp. 670-673, Oct. 2003. [14] J. Chen, R. Tanner, J. Zhang, and M. Fossorier, “Construction of Irregular LDPC Codes by Quasi-Cyclic Extension,' IEEE Transactions on Information Theory, vol. 53, no. 4, pp. 1479-1483, 2007. [15] F. Kschischang, B. Frey, and H. Loeliger, “Factor graphs and the sum-product algorithm,” IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 498-519, 2001. [16] M. Forssorier, M. Milhaljevic and H. Imai, “Reduced Complexity Iterative Decoding of Low Density Parity Check Codes Based on Belief Propagation,” IEEE Transactions on Communications, pp. 673-680, May 1999. [17] J. Heo, “Analysis of Scaling Soft Information on Low Density Parity Check Code,” Electronics Letters, vol 39, pp. 219-221, Jan. 2003. [18] J. Heo and K. Chugg, “Optimization of Scaling Soft Information in Iterative Decoding via Density Evolution Methods,” IEEE Transactions on Communications, vol. 53, pp. 957-961, Jun. 2005. [19] H. Song and P. Zhang, “Optimum Offset Factor of LDPC Codes,' Electronics Letters, vol. 39, no. 14, pp. 1065-1066, 2003. [20] E. Sharon, S. Litsyn and J. Goldberger, “An Efficient Message-Passing Scheduling for LDPC Decoding,” Proc. 23rd IEEE Convention in Tel-Aviv, pp. 223-226, Sep. 2004. [21] M. Mansour and N. Shanbag, “Low-Power VLSI Decoder Architectures for LDPC Codes”, Proc. International Symposium on Low Power Electronics and Design, pp. 284-289, 2002. [22] E. Zimmermann, P. Pattisapu, P. Bora and G. Fettweis, “Reduced Complexity LDPC Decoding using Forced Convergence,” in Proc. 7th International Symposium on Wireless Personal Multimedia Communications, Sep. 2004. [23] G. Fettweis, E.Zimmermann and W.Rave, “Forced Convergence Decoding of LDPC Codes: EXIT Chart Analysis and Combination with Node Complexity Reduction Techniques,” in Proc. 11th European Wireless Conference, Apr. 2005. [24] E. Zimmermann, P. Pattisapu, and G. Fettweis, “Bit-Flipping Post-Processing for Forced Convergence Decoding of LDPC Codes,” in Proc. 13th European Signal Processing Conference, Sep. 2005. [25] F. Kienle and N. Wehn, “Low Complexity Stopping Criterion for LDPC Code Decoders”, VTC, vol. 1, pp. 606-609, 2005. [26] D. Levin, E. Sharon, and S. Litsyn, “Lazy Scheduling for LDPC Decoding,” IEEE Communication Letters, vol. 11, No. 1, pp. 70-72, Jan. 2007. [27] W. Wang, G. Choi, “Sepculative Energy Scheduling for LDPC Decoding”, the 8th International Symposium on Quality Electronic Design, pp. 79-84, Mar. 2007. [28] Y. Li, M. Elassal, and M. Bayoumi, 'Power Efficient Architecture for (3,6)-Regular Low-Density Parity-Check Code Decoder,' Proc International Symposium on Circuits and Systems, vol. 4, pp: 23-26, May. 2004. [29] D. Hovevar, “A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes”, IEEE Workshop on Signal Processing Systems, pp. 107-112, Oct. 2004. [30] T. Brack, M. Alles, F. Kienle, N. Wehn, “A Synthesizable IP Core for WIMAX 802.16e LDPC Code Decoding,” IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, pp. 1-5, Sep. 2006. [31] T. Brack, M. Alles, T. Lehnigk-Emden, F. Kienle, N. Wehn, “Low Complexity LDPC Code Decoders for Next Generation Standards,” Design, Automation and Test in Europe Conference and Exhibition, pp. 1-6, Apr. 2007. [32] S. C. Chou, M. K. Ku and C. Y. Lin, “Switching Activity Reducing Layered Decoding Algorithm for LDPC Codes,” IEEE International Symposium on Circuits and Systems, pp. 528-531, May, 2008. [33] S. C. Chou, M. K. Ku, C. Y. Lin and Y. H. Chien, “Layered LDPC Decoder with Switching Activity Reduction,” the 19th VLSI Design/CAD Symposium, Aug. 2008. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/40152 | - |
| dc.description.abstract | 由於在行動應用裝置中低功率設計的需求愈來愈重要，我們提出了一個降低運算數目的LDPC解碼器演算法。這個演算法能夠減少必須運算的位元節點數目來減少功率消耗，並且在特定的解碼回數中會喚醒所有的節點來更新訊息以將位元錯誤率減至最低。除此之外，我們也研究了兩種更低硬體成本的衍生演算法，針對這三種演算法我們都提出了低成本的硬體架構。而模擬結果中顯示我們的演算法相較於原本的演算法最多可以減少75%最耗電的記憶體存取。而FPGA的實作結果顯示我們只增加了0.6%的硬體成本，並且在頻率140MHz時可以達到67~292Mbps的效能。 | zh_TW |
| dc.description.abstract | For the emergency of low power consumption demand in mobile applications, a decoding operation reduction algorithm for Low-Density Parity Check (LDPC) codes is proposed. Our operation reduction layered decoding algorithm reduces active node computation to lower LDPC decoder power consumption. Layered nodes are periodically refreshed to minimize coding gain degradation. Besides, two variation algorithms are also explored. Low hardware overhead partially parallel LDPC decoder architecture for all three decoding operation reduction algorithms is also described. Simulation results show that our algorithm reduces the number the most power consuming memory access operation up to 75% compared to the original layered decoding. The FPGA implementation results show that our architecture only add 0.6% hardware cost and the throughput is up to 67~292Mbps at frequency 140MHz. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-14T16:41:52Z (GMT). No. of bitstreams: 1 ntu-97-P94922003-1.pdf: 2079770 bytes, checksum: 5e3b96c745a8004ee8c15dace25b365d (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 中文摘要...................................................i
ABSTRACT..................................................ii CONTENTS.................................................iii LIST OF FIGURE............................................vi LIST OF TABLE...........................................viii Chapter 1 ntroduction......................................1 1.1 Digital Communication System Overview..................1 1.2 Low-Density Parity-Check Code Overview.................2 1.3 Motivation.............................................3 1.4 Power Consumption in Digital CMOS Circuits.............4 1.5 Thesis Organization....................................5 Chapter 2 Backgrounds......................................6 2.1 LDPC Codes.............................................6 2.1.1 Matrix Representation of LDPC Codes..................6 2.1.2 Graph Representation of LDPC Codes...................7 2.1.3 Quasi-Cyclic LDPC Codes..............................8 2.2 LDPC Decoding Algorithms...............................9 2.2.1 Sum-Product Algorithm...............................10 2.2.2 Min-Sum Algorithm...................................10 2.3 Decode Scheduling Scheme..............................15 2.3.1 Two-Phase Scheduling Scheme.........................15 2.3.2 Horizontal Layered Scheduling Scheme................16 2.3.2 Vertical Layered Scheduling Scheme..................18 2.4 Related Works of Low Power Consumption LDPC Decoder...21 2.4.1 Joint Code-Decoder Design...........................21 2.4.2 Threshold Decoding..................................21 2.4.3 Early-Termination Scheme............................22 2.4.4 Lazy Scheduling.....................................23 2.4.5 Dynamic Voltage Scaling Frequency...................23 2.4.6 Power Dissipation Analysis in LDPC Decoder..........24 Chapter 3 The Proposed Operation Reduction Layered Decoding Algorithm with Periodic Update............................25 3.1 Low Power LDPC Decoder Design Considerations..........25 3.1.1 SPA vs. MSA.........................................25 3.1.2 Horizontal Layered Scheduling Scheme vs. Vertical Layered Scheduling Scheme.................................26 3.1.3 Reduce the Computation and Memory Access of the Horizontal Layered Scheduling Scheme......................29 3.2 Low Hardware Complexity BER Compensation Scheme.......29 3.3 Scenario of the Decoding Operation Reduction Algorithm.................................................30 3.4 Formulation of the Decoding Operation Reduction Algorithm.................................................31 3.5 Variation of the Decoding Operation Reduction Algorithm.................................................33 Chapter 4 The Proposed Hardware Architecture..............36 4.1 IEEE 802.16e LDPC Code Parity-Check Matrix............36 4.2 The Decoder Architecture Overview.....................37 4.2.1 Data Path of the Decoder............................37 4.2.2 Control Unit........................................39 4.2.3 Left Rotator and Right Rotator......................39 4.2.4 Decode Processing Unit..............................39 4.3 Modification Units....................................40 4.4 Memory Structure......................................41 4.5 The Operation Reduction...............................42 4.6 Architecture of Variation Algorithms..................42 Chapter 5 Simulation and Implementation Results...........45 5.1 The FPGA Design Flow..................................45 5.1.1 System Level........................................47 5.1.2 RTL Level...........................................47 5.1.3 FPGA Level..........................................48 5.2 Algorithm Simulation Results..........................49 5.2.1 Parameter Adjustments...............................49 5.2.2 Operation Reduction of Variation Algorithms.........52 5.2.3 Performance Comparison between Algorithms...........53 5.3 FPGA Implementation Results...........................55 Chapter 6 Conclusion and Future Works.....................58 6.1 Conclusion............................................58 6.2 Future Works..........................................58 REFERENCE.................................................60 | |
| dc.language.iso | en | |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 低密度奇偶校驗碼 | zh_TW |
| dc.subject | 解碼器 | zh_TW |
| dc.subject | low-power | en |
| dc.subject | LDPC | en |
| dc.subject | decoder | en |
| dc.title | 使用降低解碼運算數目演算法之低功率IEEE 802.16e LDPC 硬體解碼器之設計與實現 | zh_TW |
| dc.title | Design and Implementation of a Low-Power IEEE 802.16e LDPC Decoder by Utilizing Decoding Operation Reduction Algorithm | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 簡韶逸(Shao-Yi Chien),楊佳玲(Chia-Lin Yang),廖俊睿(Jan-Ray Liao) | |
| dc.subject.keyword | 低密度奇偶校驗碼,低功率,解碼器, | zh_TW |
| dc.subject.keyword | LDPC,low-power,decoder, | en |
| dc.relation.page | 63 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-08-01 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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