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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 王勝德(Sheng-De Wang) | |
| dc.contributor.author | Yu-Chang Chang | en |
| dc.contributor.author | 張郁昌 | zh_TW |
| dc.date.accessioned | 2021-06-13T16:40:40Z | - |
| dc.date.available | 2006-07-06 | |
| dc.date.copyright | 2005-07-06 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-04 | |
| dc.identifier.citation | [1] G. A. Frantz, “System on a Chip: a System Perspective,” in Proceedings of Technical Papers of the 2001 International Symposium on VLSI Technology, Systems and Applications, (Hsinchu, Taiwan), pp. 1-5, 18-20 April 2001.
[2] European Space Agency, “System-On-Chip (SOC) Development,” 15 November 2004. http://www.estec.esa.nl/wsmwww/core/soc.html. [3] U. Kamath and R. Kaundin, “System-on-Chip Designs: Strategy for Success,” Dedicated Systems Magazine, p. 61, Q2 2001. http://www.dedicated-systems.com. [4] V. Kaul, “System-on-Chip: Challenges and Implementation Strategies.” news, 15 October 2001. http://frost.com. [5] Wikipedia, “Programmable logic device,” June 2005. http://en.wikipedia.org/wiki/Programmable logic device. [6] R. Hartenstein, “Are we ready for the breakthrough?,” in 10th Recongurable Architectures Workshop 2003 (RAW 2003), keynote address, (Nice, France), April 2003. [7] K. Compton and S. Hauck, “Recongurable Computing: A Survey of Systems and Software,” ACM Computing Surveys, vol. 34, no. 2, pp. 171-210, June 2002. [8] C. Wolinski, M. Gokhale, and K. McCabe, “A polymorphous computing fabric,” IEEE Micro, vol. 22, no. 5, pp. 56{68, Sep/Oct. 2002. [9] Altera Corporation, “Designing with Altera Intellectual Property Megafunctions.” http://www.altera.com/products/ip/ipm-index.html. [10] T. Rintakoski, “IP-Centric SOPC Implementation of a WCDMA Baseband Modem,” Master's thesis, Tampere University of Technology, Narva, Finland, March 2003. [11] G. De Micheli and R. K. Gupta, “Hardware/Software Co-design,” IEEE Proceedings, vol. 85, no. 3, pp. 349-365, March 1997. [12] W. Wolf, “Computers as Components : Principles of Embedded Computing System Design.” Morgan Kaufmann, 2001. [13] W. Wolf, “A Decade of Hardware/Software Codesign,” IEEE Computer, vol. 36, no. 4, pp. 38-43, April 2003. [14] K. Lahiri, A. Raghunathan, and S. Dey, “Fast performance analysis of bus-based system-on-chip communication architectures,” in Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 566-573, November 1999. [15] F. Doucet, V. Sinha, and R. K. Gupta, “Microelectronic System-on-Chip Modeling using Objects and their Relationships,” in Online Symposium for Electrical Engineers (OSEE 2000), December 2000. [16] A. Clouard, G. Mastrorocco, F. Carbognani, A. Perrin, and F. Ghenassia, “Towards Bridging the Precision Gap between SoC Transactional and Cycle Accurate Levels,” in Process Design Automation and Test in Europe (DATE 2002), March 2002. [17] A. Ferrari and A. L. Sangiovanni-Vincentelli, “System Design: Traditional Concepts and New Paradigms,” in Proceedings of International Conference on Computer Design (ICCD 1999), (Austin, TX, USA), pp. 1-12, October 1999. [18] A. Morton and W. M. Loucks, “A Hardware/Software Kernel for System on Chip Designs,” in Proceedings of the 2004 ACM Symposium on Applied Computing (SAC 2004), (New York, NY, USA), pp. 869-875, March 2004. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38653 | - |
| dc.description.abstract | Field Programmable Gate Array (FPGA) technologies enabled the implementation of customizable computing platforms using System-on-a-Programmable-Chip (SOPC), where we can
configure hardware resources appropriately to match specific application needs. In this paper, a new system design concept and a system design flow are proposed for SOPC paradigm. We describe our design and implementation of an embedded system on an SOPC development board, comparing different design methodologies and implementations using FIR application. Using the proposed design flow, the development cycle can be surprisingly short and the flexibility of SOPC can make us achieve the design specification effectively. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T16:40:40Z (GMT). No. of bitstreams: 1 ntu-94-R91921076-1.pdf: 964878 bytes, checksum: b1d99da03b5ec2eb1ad41431dd837a8a (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | 1 Introduction 1
1.1 Embedded everywhere . . . . . . . . . . . . . . . . . 1 1.2 System-on-Chip (SOC) . . . . . . . . . . . . . . . . 2 1.3 Field-Programmable Gate Arrays (FPGA) . . . . . . . . 5 1.4 System-on-Programmable-Chip (SOPC) . . . . . . . . . .9 1.5 Contributions and outline . . . . . . . . . . . . . .12 2 Challenges and new design methodology 15 2.1 Comparison of SOC and SOPC . . . . . . . . . . . . . 15 2.2 Challenges of SOC and SOPC . . . . . . . . . . . . . 18 2.3 Proposed design concept . . . . . . . . . . . . . . .23 2.4 Example design flow . . . . . . . . . . . . . . . . .26 3 Implementations of FIR filter 31 3.1 Development platform . . . . . . . . . . . . . . . . 32 3.2 Why use FIR? . . . . . . . . . . . . . . . . . . . . 37 3.3 Finite Impulse Response (FIR) . . . . . . . . . . . .40 3.4 Software implementations . . . . . . . . . . . . . . 43 3.5 Hardware implementations . . . . . . . . . . . . . . 43 4 Results comparison 49 4.1 Software implementations . . . . . . . . . . . . . . 50 4.2 Hardware implementations . . . . . . . . . . . . . . 56 4.3 Performance indexes . . . . . . . . . . . . . . . . .64 4.4 Example scenario . . . . . . . . . . . . . . . . . . 66 5 Discussions 69 5.1 Flexibility and capability of hardware accelerator . 69 5.2 The ease of design decision making . . . . . . . . . 71 5.3 Candidate applications . . . . . . . . . . . . . . . 73 6 Conclusion 79 References 81 | |
| dc.language.iso | en | |
| dc.subject | 有限脈衝響應濾波器 | zh_TW |
| dc.subject | 設計方法 | zh_TW |
| dc.subject | 硬體加速 | zh_TW |
| dc.subject | 可編程邏輯元件 | zh_TW |
| dc.subject | 可程編系統單晶片 | zh_TW |
| dc.subject | Hardware Acceleration | en |
| dc.subject | FIR | en |
| dc.subject | SOPC | en |
| dc.subject | FPGA | en |
| dc.subject | Design Methodology | en |
| dc.title | 在可程編系統單晶片上針對特定應用的設計方法 | zh_TW |
| dc.title | An Application Specific Design Methodology for System-On-a-Programmable-Chip | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 雷欽隆,陳省隆,林宗男 | |
| dc.subject.keyword | 設計方法,硬體加速,可編程邏輯元件,可程編系統單晶片,有限脈衝響應濾波器, | zh_TW |
| dc.subject.keyword | Design Methodology,Hardware Acceleration,FPGA,SOPC,FIR, | en |
| dc.relation.page | 83 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-07-04 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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