H.264畫面內編碼電路之設計與製作

Abstract

此論文提出一個H.264畫面內編碼電路的設計。此設計對編碼影像中的輝度像素可做H.264標準中所提出九種INTRA_4x4及四種INTRA_16x16的預測模式，對於彩度像素也可完成所制定的四種INTRA_CHROMA的預測模式。此設計具有處理SDTV(720 x 480 x 30 fps)應用的畫面內編碼的能力。 本文中我們設計一種可以產生所有H.264規定的預測模式的預測值產生器。H.264標準中轉換及逆轉換的電路則以多重轉換器架構加以實現。另外也設計了數量化、解數量化及模式決定電路來完成完整的編碼工作。在此設計中每一個階段均可在一個時脈同時處理四個像素。一個巨方塊將花費1350個時脈來完成所有預測模式的計算。 利用UMC 0.18微米1P6M的製程完成晶片原型設計並送至系統晶片中心進行實作。此原型設計在佈局後模擬可操作於55.56MHz、其晶片大小為2.374 x 2.434 mm2、邏輯閘數目約為201K。

In this Thesis, we propose a design of H.264 intra frame coding circuit. In the proposed design, nine INTRA_4x4 and four INTRA_16x16 prediction modes for luminance samples are realized, and four INTRA_CHROMA prediction modes for chrominance samples are also implemented. The design owns a processing capability to accomplish the H.264 intra frame coding for SDTV (720 x 480 x 30 fps) application. The architecture of intra prediction generator is designed to support all prediction modes defined in the H.264 standard. Forward/inverse transform unit proposed in [5] is adopted. Architectures of Quantization, Dequantization and Mode Decision units have also been designed. Every stage in our design can process four pixels per clock. A microblock (MB) with full prediction case will spend 1350 clocks to accomplish all prediction modes. A prototype of the proposed design was implemented in UMC 0.18um 1P6M process technology and fabricated by CIC. The maximum operation frequency of our design in post-layout simulation is 55.56 MHz. This processing capability is sufficient for the requirement in SDTV (720 x 480 x 30 fps) intra frame encoding. The die size is 2.374 x 2.434 mm2, and gate count is about 201k.