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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉深淵 | |
dc.contributor.author | Chi-Lun Lo | en |
dc.contributor.author | 羅啟倫 | zh_TW |
dc.date.accessioned | 2021-06-13T16:29:12Z | - |
dc.date.available | 2007-07-14 | |
dc.date.copyright | 2005-07-14 | |
dc.date.issued | 2005 | |
dc.date.submitted | 2005-07-12 | |
dc.identifier.citation | Bibliography
[1] J. Y. Sim, J. J. Nam, Y. S. Sohn, H. J. Park, C. H. Kim, and S. I. Cho, “A CMOS Transceiver for DRAM Bus System with a Demultiplexed Equalization Scheme,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, pp. 245-250, Feb. 2002. [2] Y. Tomita, M. Kibune, J. Ogawa, W. W. Walker, H. Tamura, and T. Kuroda, “A 10Gb/s Receiver with Equalizer and On-Chip ISI Monitor in 0.11μm CMOS,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 202-205, June 2004 [3] S. Gondi, J. Lee, D. Takeuchi, and B. Razavi, “A 10Gb/s CMOS Adaptive Equalizer for Backplane Applications,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 328–329, Feb. 2005. [4] A. X. Widmer and P. A. Franaszek, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code,” IBM J.Res. And Develop, vol. 27, pp. 440-451, Sept. 1983. [5] R. C. Walker and R. Dugan, “Low Overhead Coding Proposal for 10Gb/s Serial Links,” IEEE 802.3 High-Speed Study Group, Nov. 1999. [6] W. J. Dally and J. W. Poulton, “DIGITAL SYSTEMS ENGINEERING,” Cambridge University Press, 1998. [7] G. P. Hartman, “Continuous-Time Adaptive-Analog Coaxial Cable Equalizer in 0.5μm CMOS,” Master dissertation, University of Toronto, 1997. [8] J. N. Babanezhad, “A 3.3-V Analog Adaptive Line-Equalizer for Fast Ethernet Data Connection,” IEEE Custom Integrated Circuits Conf. Dig. Tech. Papers, pp. 343-346, May 1998. [9] B. Razavi, “Design of Integrated Circuits for Optical Communications,” McGraw Hill, International edition, 2002. [10] J. S. Choi, M. S. Hwang, and D. K. Jeong, “A 0.18-μm CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 3, pp. 419-425, MARCH 2004 [11] G. Zhang, P. Chaudhari, and M. M. Green, “A BiCMOS 10Gb/s Adaptive Cable Equalizer,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 482–483, Feb. 2004. [12] S. Galal and B. Razavi, “10Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18μm CMOS technology,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 188–189, Feb. 2003. [13] S. S. Mohan, M. M. Hershenson, S. P. Boyd, and T. H. Lee, “Bandwidth Extension in CMOS with Optimized On-Chip Inductors,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 3, pp. 346-355, MARCH 2000 [14] E. Säckinger and W. C. Fischer, “A 3-GHz 32-dB CMOS Limiting Amplifier for SONET OC-48 Receivers,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 12, pp. 1884-1888, Dec. 2000 [15] Y. Kudoh, M. Fukaishi, and M. Mizuno, “A 0.13-μm CMOS 5-Gb/s 10-meter 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, pp.741–746, May 2003. [16] M. H. Shakiba, “A 2.5 Gb/s adaptive cable equalizer,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 396–397, Feb. 1999. [17] A. J. Baker, “An Adaptive Cable Equalizer for Serial Digital Video Rates to 400Mb/s,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 174–175, Feb. 1996. [18] J. L. Zerbe, C. W. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, D. Kim, W. F. Stonecypher, A. Ho, T. P. Thrush, R. T. Kollipara, M. A. Horowitz, and K. S. Donnelly, “Equalization and Clock Recovery for a 2.5–10-Gb/s 2-PAM/4-PAM Backplane Transceiver Cell,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, pp. 2121-2129, Dec. 2003 [19] R. Farjad-Rad, C.-K. Yang, M. Horowitz, and T. Lee, “A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.35, pp. 757–764, May 2000. [20] H. Wu, J. A. Tierno, P. Pepeljugoski, J. Schaub, S. Gowda, J. A. Kash, and A. Hajimiri, “Integrated Transversal Equalizers in High-Speed Fiber-Optic Systems,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, pp. 2131-2137, Dec. 2003 [21] S. Hoyos, J. A. Garcia, and G. R. Arce, ” Mixed-Signal Equalization Architectures for Printed Circuit Board Channels,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 2, pp. 264-274, Feb. 2004 [22] S. Pavan, “Continuous-Time Integrated FIR Filters at Microwave Frequencies,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 51, NO. 1, pp. 15-20, Jan. 2004 [23] C. Pelard, E. Gebara, A. J. Kim, M. G. Vrazel, F. Bien, Y. Hur, M. Maeng, S. Chandramouli, C. Chun, S. Bajekal, S. E. Ralph, B. Schmukler, V. M. Hietala, and J. Laskar, “Realization of Multigigabit Channel Equalization and Crosstalk Cancellation Integrated Circuits,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 10, pp. 1659-1670, Oct. 2004 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38270 | - |
dc.description.abstract | 近幾年由於網際網路的普及化,伴隨著與日俱增的資料流量。高速有線通訊系統的發展成了紓解資料壅塞與促進資訊普及的最佳解決方案之一。當通訊系統的操作頻率在十億兆赫 (gigahertz) 以上的範圍時,不單單只在傳送機的前端電路的設計上會遭遇困難,資料經過傳輸通道所造成的損失是另一個需要解決的問題。等化器電路在一個資料收發機電路中扮演了一個很重要的角色,主要的功能在於將傳輸通道因為電磁效應所造成的損失做補償的動作。
這篇論文的主題是描述如何設計以及實現一個高速傳輸通道等化器電路。首先,我們將會討論三種對於傳輸通道不同的模型方法,以便之後我們等化器電路的設計。接著在論文中,我們將介紹所設計的一個高速互補式金氧半製程纜線等化器。為了不要增加額外的晶片面積,我們利用主動式電感負載來取代晶片內實現的單晶電感。資料傳輸速率可以達到3.125Gbps。最後,論文中另外描述了另一個高速互補式金氧半製程等化器的電路實作。這個設計可以用來接收並補償經過印刷電路板(PCB)後,受到寬頻訊號損失的10Gbps資料。包含了一個不須消耗直流功率卻能得到高頻增益的輸入級,以及補償PCB剩餘訊號損失的兩個串接主動濾波器。上述的兩個電路都是使用0.18μm標準互補式金氧半製程實現。 | zh_TW |
dc.description.abstract | Because of popularization of the internet network in recent years, the transmitted data quantity is growing up with each passing day. Development of high speed wired-line communication system provides one of the best solutions for solving the data jam and promoting information popularization. When the operating frequency of the communication system is beyond gigahertz range, not only the design of the transceiver front-end circuits meets difficulties but the loss of the transmission channel is another problem. An equalizer circuit plays an important role in the transceiver circuits, which is used to compensate the channel loss due to electromagnetic effects.
This thesis describes the design and implementation of the high speed transmission channel equalizer circuit. First of all, we will discuss three different techniques to model the transmission line for the design of the equalizer circuit. Next, a design of high speed CMOS coaxial cable equalizer is presented. In order not to increase the chip area, we use active inductive peaking load to replace monolithic on-chip inductor for high frequency response. This circuit can reach a data rates up to 3.125Gbps. Finally, we present another circuit implementation of a high speed CMOS equalizer. This circuit is designed to receive data rate up to 10Gbps and compensate the broadband loss of the printed-circuit-board (PCB) trace. It incorporates an input stage for high frequency gain without DC power consumption and two cascaded active filter stages for the remained frequency loss of the PCB channel. Both of the circuit designs are implemented with a standard 0.18um CMOS process. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T16:29:12Z (GMT). No. of bitstreams: 1 ntu-94-R92943005-1.pdf: 7536454 bytes, checksum: ad07ae957fcbaf2e6a6df681242fcba1 (MD5) Previous issue date: 2005 | en |
dc.description.tableofcontents | Contents
Abstract …………………………………………… I Contents …………………………………………… III List of Figures ……………………………… V List of Tables ……………………………… IX 1. Introduction 1 1.1 Wired Data Communications...........2 1.1.1 Digital Television .........2 1.1.2 Ethernet ..................3 1.1.3 High speed serial-link.....4 1.2 Motivation for Equalizers in CMOS...5 1.3 Thesis Outline...................... 6 2. Background and Channel Model..................7 2.1 Background...........................7 2.1.1 Data Coding.................7 2.1.2 8B/10B Coding...............8 2.1.3 Eye Diagram.................9 2.2 Channel Model.......................11 2.2.1 Conventional Transmission Line Model11 2.2.2 Pole/Zero transfer function curve fitting15 2.2.3 Broadband PCB T-line Model.19 3. A 3.125Gbps Coaxial Cable Equalizer..........23 3.1 Motivation..........................23 3.2 System Architecture.................23 3.3 Circuit Design and Simulation Results.25 3.3.1 Feed-forward Filter..........25 3.3.2 Slicer.......................29 3.3.3 Feed-back Block..............29 3.3.4 Output Buffer................32 3.4 Layout and Simulated Performance Summary........35 3.5 Measurement...........................36 3.5.1 Measurement Setup............36 3.5.2 Measured Eye Diagram.........37 3.5.3 Die Photograph and Performance Summary........39 4. A 10Gbps PCB Equalizer.........................41 4.1 Motivation............................41 4.2 System Architecture...................41 4.3 Circuit Design and Simulation Results.43 4.3.1 LCR Passive Filter...........43 4.3.2 Active Filter...............46 4.3.3 Pre- driver.................49 4.3.4 Output Buffer................52 4.4 Layout and Simulated Performance Summary........54 4.5 Measurement...........................55 4.5.1 Measurement Setup............55 4.5.2 Measured Eye Diagram and Bit Error Rate.....56 4.5.3 Die Photograph and Performance Summary........61 5. Conclusion and Recommendation for Future Work..63 5.1 Conclusion............................63 5.2 Recommendation for Future Work........64 Bibliography............................................67 | |
dc.language.iso | en | |
dc.title | 高速通道等化器之設計與製作 | zh_TW |
dc.title | Design and Implementation of High Speed Channel Equalizer | en |
dc.type | Thesis | |
dc.date.schoolyear | 93-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 吳介琮,李泰成,汪重光,陳巍仁 | |
dc.subject.keyword | 高速有線通訊系統,傳輸通道,訊號補償,等化器, | zh_TW |
dc.subject.keyword | high speed wired-line communication system,transmission channel,siganl compensation,equalizer, | en |
dc.relation.page | 70 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2005-07-13 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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