利用正規化解決緩衝器置入問題

Abstract

隨著超大型積體電路製程的進步，緩衝器置入技術成為提昇效能的要角。現有的研究(如：VGDP演算法)主要專注在演算法效率上，我們則是著重在效能上的精進。不同於以往以動態規劃為基礎的演算法，我們利用正規化的方式來解決緩衝器置入的問題。我們所提出的正規化緩衝器置入演算法，可以更進一步的增進以路徑為基礎VGDP演算法的結果。實驗結果顯示，我們的演算法在ISCAS 85的電路上，平均有 7.64 % 的電路延遲改善。

Along with the progress of VLSI technology, buffer insertion plays an increasingly important role in improving circuit performance. Prior works (e.g. VGDP algorithm) are focused on enhancing the running time of buffer insertion algorithms, while our main objective in this thesis is to improve the solution quality. In contract to the traditional dynamic programming algorithms, we propose a formal-assisted buffer insertion (FABI) algorithm which can further improve circuit delay optimized by path-based VGDP buffer insertion. Experimental results show that block-based FABI has average 7.64 % circuit delay improvement over the path-based VGDP on ISCAS 85 benchmark circuits.