在多閾值互補式金屬氧化物半導體設計中提供有效率的能量管理流程

Abstract

在先進的深次微米 (deep sub-micron) 互補式金屬氧化物半導體設計製程中,漏電流 (leakage current) 以指數的速度在成長,在 65 奈米的製程上,漏電流在整個能量的消耗上更佔了幾乎接近50 %。由於奈米製程持續進化而且嵌入式系統待機時間往往較長，因此對於降低漏電的性能要求更加嚴苛，但目前在持續邁向更先進製程的發展下，漏電量將成為一大隱憂,所以如何防堵漏電問題成了一大關鍵。在許多提出減少能量消耗的理論中, 電源閘控制 (power gating) 算是最有效降低能量消耗的方法. 電源閘控制有很多種設計方式，在目前，分散式休眠電晶體系統 (Distributed Sleep Transistor Network)是最常被工業界採用的一種設計方式，在本論文中,我們提出一個方法來減少打開整體休眠電晶體的覺醒時間(Wake-up time),在所能容忍的急速電流(rush current)的限制下,並且可以降低能量的消耗。由實現結果顯示, 我們所提出的方法確實可以達到降低覺醒時間和減少電壓的壓降。以實驗數據的平均來說,覺醒時間有大約16.84%的降低;電壓的壓降則有20.25%的減少。

In the deep sub-micron CMOS technology, leakage current increases so exponentially that it becomes a significant drain on the total power consumption. In the 65 nanometer process, leakage current is expected to reach 50% of total power consumption. Due to the fact that the nanometer process changes rapidly and the embedded system has long active time, it is explicitly needed to reduce leakage power in a design. Currently, the biggest concern in the advanced technology is how to reduce the leakage power. Among various leakage reduction techniques, the power-gating technique has become one of the most effective methods in reducing leakage power in low-power designs. During the power mode transition, large rush currents may lead to malfunctions in a power gating design. Currently, many industrial power-gating designers adopt the Distributed Sleep Transistor Network (DSTN) structure to reduce rush currents. In our research, we propose an efficient method to reduce wake-up time and power consumption during the rush current constraint. Experiments show that the proposed method can effectively reduce wake-up time and improve IR drops, around 16.84% reduction in wake-up time and 20.25% reduction in IR drops on average.