區段加權亂數低功率自我測試之基頻數位接收機之研製

Abstract

這篇論文提出了區段加權亂數之低功率自我測試技術。此技術將掃瞄鏈區分為不同權重的區段。權重較高的區段相較於權重較輕的區段，有較高的機率出現固定的位元值。權重高的區段較靠近掃瞄鏈輸出端，而權重較輕的區段較靠近掃瞄鏈輸入端。藉由此方法最低化測試圖樣輸入時的邏輯轉換。除此之外，藉由將每一區段中的掃瞄單元重排，可更進一步減低掃瞄輸出時的邏輯轉換。在ISCAS電路上實驗的結果，相較於傳統自我測試技術，區段加權亂數自我測試技術可以減少74%的功率消耗。區段加權亂數自我測試的電路非常小，而且不會隨著待測電路變大而有大幅度的增加。此技術需要付出的代價是掃瞄鏈重排的額外的面積和繞線。

This thesis proposes a segment weighted random (SWR) BIST technique for low power testing. This technique divides the scan chain into segments of different weights. Heavily weighted segments have more biased probability than lightly weighted segments. Heavily weighted segments are placed closer to the end of scan chain than the lightly weighted segments so the scan-in transitions are minimized. In addition, scan cells in segments of the same weight are reordered to further reduce the scan-out transitions. The penalty of this technique is area and routing overhead for scan chain reordering. This thesis also presents a low power DSSS digital receiver design. The modulation scheme is QPSK. The receiver obtains partial symbols form the analog correlator. The receiver consists of two major blocks: CFO estimator and carrier recovery loop. The feature of this receiver is that it eliminates the carrier frequency offset (CFO) and the timing offset (TO). The receiver implements the proposed SWR-BIST technique. The simulation results show that in the functional mode, the power consumption is 3.18mW in average. In the BIST mode, the power consumption of SWR-BIST is 6.35mW (at 16MHz clock), which is 40% lower than that of the traditional BIST (10.49mW). The receiver is implemented in UMC 0.18μm 1P6M technology. The measurement results confirm the effectiveness of the SWR-BIST.