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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Chun-Yi Lee | en |
| dc.contributor.author | 李濬屹 | zh_TW |
| dc.date.accessioned | 2021-06-13T07:57:51Z | - |
| dc.date.available | 2006-07-28 | |
| dc.date.copyright | 2005-07-28 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-23 | |
| dc.identifier.citation | [Alyamani 03] A. A. Al-Yamani, and E. J. McCluskey, “Built-In Reseeding for Serail BIST,” IEEE Proceedings - VLSI Test Symposium, pp.63 - 68, 2003.
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Peng, R.Ubar, “Test cost minimization for hybrid BIST,” IEEE Proceedings - International Symposium on Defect and Fault Tolerance in VLSI Systems, 25-27 Oct, pp. 283 - 291, 2000. [Konemann 91] B. Konemann, “LFSR-Coded Test Patterns for Scan Designs,” IEEE Proceedings - European Test Conference, pp.237-242, 1991. [Lee 05a] Chun-Yi Lee and James Chien-Mo Li, “Segment Weighted Random BIST (SWR-BIST): A Low Power BIST Technique,” IEEE Proceedings – Asian Solid State Circuits Conference (A-SSCC) 2005. [Lee 05b] Chun-Yi Lee and James Chien-Mo Li, “Segment Weighted Random BIST (SWR-BIST): A Low Power BIST Technique,” The 16th VLSI Design / CAD Symposium. [Lee 05c] Chun-Yi Lee and James Chien-Mo Li, “Segment Weighted Random BIST (SWR-BIST) Technique for Low Power Testing,”, Bulletin of the College of Engineering, N.T.U., NO. 93, February 2005, pp. 55-64. [Lai 04] L. Lai, J. H. Patel, T. Rinderknecht, and W. T. Cheng, “Logic BIST with Scan Chain Segmentation,” IEEE Proceedings - International Test Conference, pp.57 - 66, 2004. [Li 04] Li, J. C.M, “A Design for Testability Technique for Low Power Delay Fault Testing,” IEICE Transactions on Electronics, v E87-C, n 4, April, 2004, pp. 621 - 628 [Lin 03] X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, and B. Swanson, N. Tamarapalli, “High-frequency, at-speed scan testing,“ IEEE Transactions on Design and Test of Computers, Vol. 20, No. 5, September/October, pp. 17 - 25, 2003. [Pouya 00] B. Pouya and A. L. Crouch, “Optimization Trade-offs for Vector Volume and Test Power,” IEEE Proceedings - International Test Conference, pp. 873 - 881, 2000. [Power Compiler 02] Power Compiler User Guide Manual, Synopsys, Release 2002.05, May 2002, ch2. [Sankaralingam 01] R. Sankaralingam, B. Pouya and N. A. Touba, “Reducing Power Dissipation During Test Using Scan Chain Disable,” IEEE Proceedings - VLSI Test Symposium, pp. 319 - 324, 2001. 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Wang, “Generation of Low-Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST,” IEEE Proceedings - International Test Conference, pp. 834 - 843, 2002. [Whetsel 00] L. Whetsel,” Adapting scan architectures for low power operation” IEEE Proceedings - International Test Conference, 2000, pp. 863 - 872. [Zhang 99] X. Zhang, K. Roy, and S. Bhawmik, “POWERTEST: A tool for Energy Conscious Weighted Random Pattern Testing, “IEEE Proceedings - International Conference on VLSI Design, pp. 416 - 422, 1999. [Zorian 93] Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Design,” IEEE Proceedings - VLSI Test Symposium, pp. 4 - 9, 1993. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/36349 | - |
| dc.description.abstract | 這篇論文提出了區段加權亂數之低功率自我測試技術。此技術將掃瞄鏈區分為不同權重的區段。權重較高的區段相較於權重較輕的區段，有較高的機率出現固定的位元值。權重高的區段較靠近掃瞄鏈輸出端，而權重較輕的區段較靠近掃瞄鏈輸入端。藉由此方法最低化測試圖樣輸入時的邏輯轉換。除此之外，藉由將每一區段中的掃瞄單元重排，可更進一步減低掃瞄輸出時的邏輯轉換。在ISCAS電路上實驗的結果，相較於傳統自我測試技術，區段加權亂數自我測試技術可以減少74%的功率消耗。區段加權亂數自我測試的電路非常小，而且不會隨著待測電路變大而有大幅度的增加。此技術需要付出的代價是掃瞄鏈重排的額外的面積和繞線。 | zh_TW |
| dc.description.abstract | This thesis proposes a segment weighted random (SWR) BIST technique for low power testing. This technique divides the scan chain into segments of different weights. Heavily weighted segments have more biased probability than lightly weighted segments. Heavily weighted segments are placed closer to the end of scan chain than the lightly weighted segments so the scan-in transitions are minimized. In addition, scan cells in segments of the same weight are reordered to further reduce the scan-out transitions. The penalty of this technique is area and routing overhead for scan chain reordering.
This thesis also presents a low power DSSS digital receiver design. The modulation scheme is QPSK. The receiver obtains partial symbols form the analog correlator. The receiver consists of two major blocks: CFO estimator and carrier recovery loop. The feature of this receiver is that it eliminates the carrier frequency offset (CFO) and the timing offset (TO). The receiver implements the proposed SWR-BIST technique. The simulation results show that in the functional mode, the power consumption is 3.18mW in average. In the BIST mode, the power consumption of SWR-BIST is 6.35mW (at 16MHz clock), which is 40% lower than that of the traditional BIST (10.49mW). The receiver is implemented in UMC 0.18μm 1P6M technology. The measurement results confirm the effectiveness of the SWR-BIST. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T07:57:51Z (GMT). No. of bitstreams: 1 ntu-94-R92943140-1.pdf: 1094401 bytes, checksum: b20f751ea9c680f83739f224ed16097b (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | Abstract II
Acknowledgements III Table of Contents IV List of Figures VII List of Tables X Chapter 1. Introduction 1 1.1 Motivation of Low Power BIST 1 1.2 Low Power Communication SOC 2 1.3 Contributions 4 1.4 Thesis Organization 4 Chapter 2. Background 5 2.1 Low Power Testing 5 2.1.1 Previous Work 5 2.1.2 NTSC and NTSI 14 2.2 The 5.2GHz Low Power BISTable Communication SOC 15 Chapter 3. Segment Weighted Random BIST (SWR-BIST) 17 3.1 Scan Input Power Reduction 18 3.1.1 SWR-BIST Architecture 18 3.1.2 Balance Ratio and Segment Partition 20 3.2 Scan Output Power Reduction 23 3.2.1 Greedy Algorithm 23 3.2.2 Simulated Annealing 24 3.3 Design Flow 27 Chapter 4. Receiver Design 29 4.1 System Overview 29 4.1.1 Transceiver System Architecture 30 4.1.2 Packet Format 32 4.2 Receiver Architecture 32 4.2.1 CFO Estimator 34 4.2.2 Carrier Recovery Loop 37 4.2.3 Differential Decoder 43 4.2.4 Timing Offset Estimator 43 4.2.5 Controller 45 4.3 BIST Architecture 47 Chapter 5 Experimental Results 51 5.1 SWR-BIST on ISCAS Benchmark Circuits 51 5.1.1 Fault Coverage and Power Dissipation 51 5.1.2 Overhead 55 5.2 Receiver 57 5.2.1 Bit Error Rate 57 5.2.2 Power Consumption and Fault Coverage 58 5.2.3 Area Overhead 58 5.3 Chip 59 5.3.1 Layout 59 5.3.2 Chip Measurement 62 Chapter 6. Discussions and Future Work 70 6.1 Discussions 70 6.1.1 Placement and Routing Consideration 70 6.1.2 Inversion at Data Input 72 6.1.3 Deterministic BIST 72 6.2 Future Work 73 6.2.1 SWR-BIST Reseeding 73 6.2.2 Test Data Reduction for SOC Wrapper 73 Chapter 7. Summary 74 References 75 | |
| dc.language.iso | en | |
| dc.subject | 低功率自我測試 | zh_TW |
| dc.subject | 基頻數位接收機 | zh_TW |
| dc.subject | Low Power BIST | en |
| dc.subject | Baseband Receiver | en |
| dc.title | 區段加權亂數低功率自我測試之基頻數位接收機之研製 | zh_TW |
| dc.title | Design and Implementation of A Low Power Self-Testable Baseband Receiver Using Segment Weighted Random BIST | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃俊郎(Jiun-Lang Huang),闕志達(Tzi-Dar Chiueh) | |
| dc.subject.keyword | 低功率自我測試,基頻數位接收機, | zh_TW |
| dc.subject.keyword | Low Power BIST,Baseband Receiver, | en |
| dc.relation.page | 78 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-07-24 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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