高速網路可程式化數位邏輯傳收模組之研製

Abstract

摘要 對於發展高速網路系統，設計一個符合需求的「高速網路可程式化數位邏輯傳送接收之測試平台」是必要的，雖然現今市面上OC-192的傳收晶片（transceiver ICs）的產品己相當成熟，但對於可提供晶片設計平台之商用產品，卻付之闕如。於是本論文將對高速可程式化傳送接收之測試平台的設計與實作，提出開發的方法和實作之成果，以供日後發展高速網路與光通訊之用。 本測試平台選用Xilinx公司的場規劃可程式陣列閘（Field Programmable Gate Arrays，FPGA）XC2VP70晶片和AMCC公司所設計符合SONET STS-192標準之16：1與1：16 S19237傳收晶片。XC2VP70具有20組可傳收高達3.125 Gb/s的信號之Rocket I/O埠，晶片腳位多達1704，而且S19237晶片包含16：1和1：16多工�解多工傳收器（ Multiplexing / DeMultiplexing Transceiver ）的功能是具有傳送與收接10 Gb/s信號的能力。高速數位電路的信號完整性（Signal Integrity）亦是主要的設計考量重點，分別藉由高速電路信號完整性的模擬軟體工具「ADS（Advance Design System）」及傳輸線特徵阻抗的試算軟體「Polar」來設計10 Gb/s與625 Mb/s之高速傳輸線。使得高速信號能在印刷電路板中傳輸時，其信號能維持一定有效的品質。 在驗證與量測方面，使用硬體描述語言在FPGA上建立偽隨機碼（Pseudo Random Bit Sequences，PRBS）產生器，產生16組625 Mb/s的信號並行傳送16：1 MUX，進而產生一10 Gb/s PRBS之信號，再由數位通訊分析儀（Digital Communication Analyzer，DCA）量測其眼狀圖，使本測試平台的10 Gb/s傳輸功能得到驗證。

Abstract For developing high speed networking, it is necessary to design a high speed programmable networking testing platform that meets our requirement. Currently, OC-192 transceiver ICs are mature product, but no commercial product to provide chip design platform. Therefore, this thesis presents the developing methods and the implementation results for the design and implement of the high speed programmable networking testing platform. The FPGA XC2VP70 chip from Xilinx and 16:1 and 16:1 S19237 transceiver chip from AMCC conformed to SONET STS-192 standard are used to design the high speed programmable networking testing platform. With 1704 pins, the FPGA in XC2VP70 has 20 ports that are able to transmit and receive high speed signals up to 3.125 Gb/s. S19237 chip has the function of 16:1 and 1:16 MUX/DeMux for the transmission and receiving of 10 Gb/s signal. The circuit design is complex and challenging with special requirement of the signal integrity. By using the simulation tools, such as ADS (Advance Design System) and control transmission line characteristic impedance software “Polar”, we are able to design 10 Gb/s and 625 Mb/s high speed transmission lines. The high speed signals can be transmitted in the PCB with acceptable signal quality. In the verification and measurement, the PRBS generator inside FPGA generates sixteen 625 Mb/s signals and these parallel signals are transmitted to the 16:1 MUX, and the MUX outputs a 10 Gb/s PRBS signal. And the eye pattern are measured via DCA ( Digital Communication Analyzer ) to verify the 10 Gb/s transmission ability of this testing platform.