使用新穎輸入阻抗匹配技巧的鏡像訊號消除CMOS低雜訊放大器之設計

Abstract

使用互補式金氧半導體（CMOS）技術來設計射頻（radio frequency）無線電路在最近幾年受到了很大的注意，已經有很多相關領域的設計技巧、著作發表在雜誌、期刊上。低雜訊放大器（low noise amplifier）是射頻電路中的基本建構方塊，然而輸入阻抗匹配（input impedance matching）的問題通常都被過渡簡化，或是基於一些共識而省略不談；因此高頻率的低雜訊放大器在設計上變得耗費時間。在這篇論文中，我們探討了串疊式（cascode）CMOS低雜訊放大器的輸入阻抗匹配的困難所在，並提出一個明確的設計方法，使得輸入阻抗的設計變得有方向可循，而不需要經由嘗試錯誤的方法。除了輸入阻抗的問題外，傳統的超外插（superheterodyne）收發器（transceiver）使用許多的離散式（discrete）帶通濾波器（band-pass filter）因而使得電路無法進一步整合到單一晶片上，因此本論文的另一個設計目標是將點拒濾波器（notch filter）整合到超外插收發器裏面。 我們在這篇論文中使用一個新的技巧來設計鏡像訊號消除（image-reject）的串疊式CMOS低雜訊放大器。除了先前所提的輸入阻抗匹配方法之外，我們也提出並分析具有高的鏡像訊號消除能力的4階T型結構的點拒濾波器。我們在本論文中採用重複使用電流的技巧來節省電源功率並用以提高輸出功率增益，同時使用台積電的0.18微米製程來設計一個應用於2.4 GHz、具有高的鏡像訊號消除能力的低雜訊放大器來驗證所提出的電路架構。使用晶圓廠的元件模型得到的模擬結果顯示在1.7 GHz的鏡像頻率可達到 32 dB的鏡像消除能力，而在2.4 GHz的操作頻率具有19 dB的輸出增益。整個電路操作在1.5 V的電壓，消耗功率是4.6毫瓦(mW)。

The design of radio frequency (RF) circuits using CMOS technology has gained many focuses in recent years. Many fantastic design techniques have been published in many literatures. Low noise amplifier (LNA) is one of the well-studied building block for RF circuits. However, the basic problem of input matching have been oversimplified or sometimes even ignored by common assumption. This makes the design of a high frequency LNA be time-consuming. In this dissertation, the difficulty of the input matching for cascode CMOS LNA is explored and a design methodology is proposed to achieve input matching in an explicit approach. In addition to the input matching problem, another design goal is the integration of image-reject (IR) filter for superheterodyne transceivers since the external band-pass filter prevents further integration for RF circuits. A new design technique for image-reject CMOS low-noise amplifiers (LNAs) is presented in this dissertation. In addition to the proposed input matching method, a passive notch filter with high image-reject ability is analyzed. This improved design technique uses a 4th-order symmetric T-coil notch filter to achieve image-reject function. Current reuse technique is adapted in the proposed technique to save power and to boost power gain. A 2.4 GHz image-reject LNA is designed with TSMC 0.18 μm CMOS process to demonstrate the potentially high image-reject ability of the proposed architecture. Simulation results using available foundry models show about 32 dB image rejection at 1.7 GHz. The power gain of the design is 19 dB and the total power consumption is about 4.6 mW at 1.5 V power supply.