以序列組表示法實踐系統晶片測試排程

Abstract

伴隨著系統晶片設計的複雜與多元化，系統晶片的測試排程也變成了一個需要被認真考慮的課題。ㄧ個好的測試排程可以大幅的縮短總測試時間。一般在探討測試排程的時候，通常要考慮到功率的損耗、匯流排的指定、與個別測試的測試時間。因此，測試排程的問題可以當成三維的封裝問題來思考。 在這篇論文中，我們採用序列組表示法合併模擬退火法的方法來架構基本的框架藉以實踐系統晶片的測試排程。遵循著`最短優先`的概念原則，我們提出我們的初始排程方法而不採用隨機產生一個合法解的方式，因為對於我們的限制來說，若隨機產生的話會耗費太多時間在產生合法解上面。除此之外，序列組表示法所產生的「樹結構」在此時也被我們拿來當作檢驗各種限制條件的方法。由實驗的結果可知，藉由我們的方法可以在合理的時間內得到比較好的解。

With the growing complexity of SOC designs, the SOC test scheduling problem becomes a great issue. A good test scheduling can greatly decrease the total test time. When we investigate the scheduling problem, the power consumption, TAM bus assignment, and individual test time must all be considered. Hence, the test scheduling can be thought as the 3-D bin packing problem. In this thesis, we adopt the Sequence-Pair representation combining with the Simulated-Annealing process to construct the basic frame. Using the shortest-first concept, we proposed our initial scheduling method to generate a legal result instead of generating it randomly which is experimentally proven to be time wasting. Besides, the tree graph comprehended in Sequence-Pair is used to check the constraints when doing perturbations. The experimental results show that we can obtain a better solution within an acceptable run time by our proposed algorithm.