使用線性模型來評估快閃式類比數位轉換器的內建自我測試器在製程變異下的效能

Abstract

隨著IC製程邁向奈米時代，電路的面積更小、密度更高、速度更快，讓外接測試機台的成本也愈來愈高。因此，可測試性設計(Dft, Design for Test)技術，成為市場接受度越來越高的解決方案。然而，雖然在數位方面可測試性設計的技術已經十分的成熟，類比方面的接受度還有待提升。主要的問題在於(1)缺乏可靠的方法來評估技術好壞，(2)模擬時間太長。除此之外，一般的內建自我測試電路，都與待測電路一樣，受到製程變異的影響。這讓評估DfT技術更加地困難。 在這篇論文中，我們提出了一套方法來評估內建測試電路在製程變異下的效能。這個方法考慮了製成變數之間的相關性，所以能得到更準確的模擬結果。我們實做了一套自動化評估工具，並用一個內建自我測試電路的6-bit快閃式類比數位轉換器來做驗證。我們也利用線性模型，提出了一個加速的方法。實驗結果顯示，新方法比原本的蒙地卡羅方法快了大約一百倍左右。

As today’s IC technology continues moving forward nanometer era, the cost of using external testers to distinguish between faulty and good circuits has risen to an unacceptable high level. Therefore, DfT (Design-for-Test) techniques have prevailed in recent years. However, unlike their digital counterparts, the Analog DfT techniques are far from being widely adopted. The main reasons are (1) lack of reliable method to evaluate DfT techniques, and (2) the time-consuming simulation process. Besides, the BIST (Built-in Self Test) circuit suffers the same process variation effects as its DUT (Device under Test) circuit. This fact makes evaluating BIST performance more difficult. In this thesis, we propose a method to evaluate BIST performance under process variation. The correlations between process parameters are considered, and simulation result is more close to real life. An automation evaluation tool is implemented, and a 6-bit flash ADC with a static ramp BIST is utilized as testing vehicle. We also introduce a novel methodology for accelerating the evaluation process of flash ADC. The experimental result shows that the new method is about hundred times faster than the Monte Carlo method.