低伏導管式類比數位轉換器和 採用可適性濾波技術之數位校準方法

Abstract

In recent years, with the rapid growth of information the speed of data rate in communication system needs to be improved. Therefore different architectures of transceiver have been presented for the solution and as the CMOS technology is evolving, those impractical method before now become realizable. In modern trend of SOC, most of the transceiver will adopt a high-speed and high dynamic range ADC in its system block. For example, in the RF system, more emphases are made on the integration and adaptability. For monolithic integration, a homodyne receiver is more suitable. By its feature of channel selection in base-band, the wanted signal channel and detected signal sensitivity can be adapted by using the digital filtering techniques after the zero-IF signal digitized by the ADC. Pipelined ADC is the most suitable architecture since it features of high speed and can have high dynamic range. Besides, with bootstrapping techniques and power optimization, the low voltage operation and low power consumption can be demonstrated. This thesis will show how to implement a 10-bit pipelined ADC operating under 2.5V supply voltage by using standard TSMC 0.35um CMOS technology and the measurement result. Because the threshold voltage of this technology is not that of the low-threshold voltage process, the design of OPAMP should be careful. The reason is that the NMOS and PMOS in cascade topology are operating near the boundary of saturation which is close to triode region. This may make the OPAMP not have gain high enough. To solve this problem a digital calibration method will be presented. It’s just like an adaptive equalizer to calibrate the nonlinear transfer curve of ADC’s input and output that resulted from non-ideal stage gain. With this method, a ADC suffered from distortion can be compensated so that its linearity will become better. .