ARM 指令相容的RISC 微處裡器 設計

Abstract

此篇論文討論ARM指令相容之精簡指令集處理器設計，此處理器以3級管線化設計之，包含存取指令，解碼，和執行等三級。此處理器設計包含了44個輸入接腳及79個輸出接腳，資料及定址匯流排則為32位元，最高運算速度可達90MHz。此晶片設計以0.18製程製造。

We are going to see the design process of a RISC processor for ARM instructions. The processor is pipelined into 3 stages; fetch, decode and execute. There are 44 input and 79 output pins, excluding the power connections. The data and address bus are both 32-bit. Highest frequency is 90MHz with 0.18 CMOS technology. The processor supports virtual memory systems. Instruction set covers branch and branch with link, data processing, program status register transfer, multiply and multiply accumulate, single data transfer, block data transfer, single data swap, software interrupt, coprocessor data operations, coprocessor data transfers, coprocessor register transfers and undefined instruction. We will start with building a general idea about the architecture and IO signals of the processor. Then we will see the instruction set of the processor including the binary encoding of the instructions. We will examine the organization of the components of the processor in third chapter. Fourth chapter is about design flow ie, the transformation of the design from an RTL code into a physical chip. In fifth chapter we will se the simulation results of post-layout design. Then we will end up with the conclusion.